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https://github.com/Fennix-Project/Kernel.git
synced 2025-05-28 15:34:33 +00:00
Changed SMP code
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Alex
parent
7f47b2a3a4
commit
fa92676d9f
GPG Key ID:
EACC3AD603BAB4DD
@ -220,7 +220,7 @@ namespace APIC
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Timer::Timer(APIC *apic) : Interrupts::Handler(CPU::x64::IRQ0)
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{
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trace("Initializing APIC timer on CPU %d", CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE));
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trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
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this->lapic = apic;
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this->lapic->Write(APIC_TDCR, 0x3);
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@ -259,7 +259,7 @@ namespace APIC
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this->lapic->Write(APIC_TIMER, (long)CPU::x64::IRQ0 | (long)APIC_PERIODIC);
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this->lapic->Write(APIC_TDCR, 0x3);
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this->lapic->Write(APIC_TICR, TicksIn10ms / 10);
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trace("APIC Timer (CPU %d): %d ticks in 10ms", CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), TicksIn10ms / 10);
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trace("APIC Timer (CPU %d): %d ticks in 10ms", GetCurrentCPU()->ID, TicksIn10ms / 10);
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KPrint("APIC Timer: %d ticks in 10ms", TicksIn10ms / 10);
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}
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@ -31,46 +31,21 @@ volatile bool CPUEnabled = false;
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#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
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static __attribute__((aligned(PAGE_SIZE))) CPUData CPUs[MAX_CPU] = {0};
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CPUData *GetCPU(uint64_t id) { return &CPUs[id]; }
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CPUData *GetCurrentCPU()
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{
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uint64_t ret = 0;
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#if defined(__amd64__)
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ret = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
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#elif defined(__i386__)
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#elif defined(__aarch64__)
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#endif
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if (!CPUs[ret].IsActive)
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{
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error("CPU %d is not active!", ret);
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return &CPUs[0];
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}
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if (CPUs[ret].Checksum != CPU_DATA_CHECKSUM)
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{
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error("CPU %d data is corrupted!", ret);
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return &CPUs[0];
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}
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return &CPUs[ret];
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}
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CPUData *GetCPU(long id) { return &CPUs[id]; }
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CPUData *GetCurrentCPU() { return (CPUData *)CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE); }
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extern "C" void StartCPU()
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{
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CPU::Interrupts(CPU::Disable);
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CPU::InitializeFeatures();
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uintptr_t CoreID = CORE;
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CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, (int)*reinterpret_cast<int *>(CoreID));
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uint64_t CPU_ID = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
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uint64_t CoreID = (int)*reinterpret_cast<int *>(CORE);
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// Initialize GDT and IDT
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Interrupts::Initialize(CPU_ID);
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Interrupts::Enable(CPU_ID);
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Interrupts::InitializeTimer(CPU_ID);
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Interrupts::Initialize(CoreID);
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Interrupts::Enable(CoreID);
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Interrupts::InitializeTimer(CoreID);
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CPU::Interrupts(CPU::Enable);
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KPrint("CPU %d is online", CPU_ID);
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KPrint("CPU %d is online", CoreID);
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CPUEnabled = true;
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CPU::Stop(); // Stop and surpress interrupts.
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}
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@ -109,7 +84,7 @@ namespace SMP
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memcpy((void *)TRAMPOLINE_START, &_trampoline_start, TrampolineLength);
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POKE(volatile uint64_t, PAGE_TABLE) = CPU::x64::readcr3().raw;
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POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPage();
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POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
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POKE(volatile uint64_t, CORE) = i;
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asm volatile("sgdt [0x580]\n"
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@ -124,6 +99,7 @@ namespace SMP
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;
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trace("CPU %d loaded.", ((ACPI::MADT *)madt)->lapic[i]->APICId);
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KernelAllocator.FreePages((void *)*reinterpret_cast<long *>(STACK), TO_PAGES(STACK_SIZE));
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CPUEnabled = false;
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}
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else
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@ -177,8 +177,6 @@ namespace CPU
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{
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#if defined(__amd64__)
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static int BSP = 0;
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if (!BSP)
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CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, 0);
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CPU::x64::CR0 cr0 = CPU::x64::readcr0();
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CPU::x64::CR4 cr4 = CPU::x64::readcr4();
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uint32_t rax, rbx, rcx, rdx;
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@ -3,6 +3,7 @@
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#include <display.hpp>
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#include <printf.h>
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#include <debug.h>
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#include <smp.hpp>
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#include <cpu.hpp>
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#if defined(__amd64__)
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@ -215,8 +216,7 @@ namespace CrashHandler
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}
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}
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EHPrint("\e7981FCTechnical Informations on CPU %lld:\n",
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CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE));
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EHPrint("\e7981FCTechnical Informations on CPU %lld:\n", GetCurrentCPU()->ID);
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EHPrint("FS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx\n",
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CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE),
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Frame->ss, Frame->cs, Frame->ds);
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@ -54,9 +54,6 @@ EXTERNC void Entry(BootInfo *Info)
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BootClock.Hour, BootClock.Minute, BootClock.Second,
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BootClock.Day, BootClock.Month, BootClock.Year);
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KPrint("CPU: \e8822AA%s \e8888FF%s (\e058C19%s\e8888FF)", CPU::Vendor(), CPU::Name(), CPU::Hypervisor());
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GetCPU(0)->ID = 0;
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GetCPU(0)->IsActive = true;
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GetCPU(0)->Checksum = CPU_DATA_CHECKSUM;
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KPrint("Initializing GDT and IDT");
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Interrupts::Initialize(0);
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KPrint("Initializing CPU features");
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@ -86,5 +83,6 @@ EXTERNC void Entry(BootInfo *Info)
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SMP::Initialize(PowerManager->GetMADT());
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KPrint("\e058C19######## \eE85230END \e058C19########");
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CPU::Interrupts(CPU::Enable);
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// asm("int $0x1");
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CPU::Stop();
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}
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@ -35,6 +35,7 @@ extern uint64_t _kernel_text_end, _kernel_data_end, _kernel_rodata_end;
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#define TO_GPB(d) (d / 1024 / 1024 / 1024 / 1024 / 1024 / 1024 / 1024 / 1024 / 1024 / 1024)
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#define PAGE_SIZE 0x1000
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#define STACK_SIZE 0x10000
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// to pages
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#define TO_PAGES(d) (d / PAGE_SIZE + 1)
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@ -5,35 +5,40 @@
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/** @brief Maximum supported number of CPU cores by the kernel */
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#define MAX_CPU 256
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#define CPU_DATA_CHECKSUM 0xC0FFEE
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struct CPUArchData
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{
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#if defined(__amd64__)
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int stub;
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/* TODO */
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#elif defined(__i386__)
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#elif defined(__aarch64__)
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#endif
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};
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struct CPUData
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{
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/**
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* @brief CPU ID.
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*/
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uint64_t ID;
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/**
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* @brief Local CPU error code.
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*/
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/** @brief Used by syscall handler */
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uint8_t *SystemCallStack; /* gs+0x0 */
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/** @brief Used by syscall handler */
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uint64_t TempStack; /* gs+0x8 */
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/** @brief Used by CPU */
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uint64_t Stack;
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/** @brief CPU ID. */
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long ID;
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/** @brief Local CPU error code. */
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long ErrorCode;
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/**
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* @brief Is CPU online?
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*/
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/** @brief Is CPU online? */
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bool IsActive;
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/**
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* @brief Architecture-specific CPU data.
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*/
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void *Data;
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/**
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* @brief Checksum. Used to verify the integrity of the data. Must be equal to CPU_DATA_CHECKSUM (0xC0FFEE).
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*/
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/** @brief Architecture-specific CPU data. */
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CPUArchData *Data;
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/** @brief Checksum. Used to verify the integrity of the data. Must be equal to CPU_DATA_CHECKSUM (0xC0FFEE). */
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int Checksum;
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} __attribute__((packed));
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CPUData *GetCurrentCPU();
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CPUData *GetCPU(uint64_t ID);
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CPUData *GetCPU(long ID);
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namespace SMP
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{
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