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https://github.com/Fennix-Project/Kernel.git
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Implemented GDT & IDT
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387
include/cpu.hpp
387
include/cpu.hpp
@ -8,167 +8,256 @@
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*/
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namespace CPU
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{
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/**
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* @brief Enum for CPU::Interrupts() function.
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*/
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enum InterruptsType
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{
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/**
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* @brief Enum for CPU::Interrupts() function.
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* @brief Check if interrupts are enabled.
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*/
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enum InterruptsType
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Check,
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/**
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* @brief Enable interrupts.
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*/
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Enable,
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/**
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* @brief Disable interrupts.
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*/
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Disable
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};
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/**
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* @brief Get CPU vendor identifier.
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*
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* @return char* CPU Vendor ID.
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*/
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char *Vendor();
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/**
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* @brief Get CPU name.
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*
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* @return char* CPU Name.
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*/
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char *Name();
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/**
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* @brief Get CPU hypervisor vendor.
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*
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* @return char* Hypervisor vendor.
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*/
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char *Hypervisor();
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/**
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* @brief Pause the CPU
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*/
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void Pause();
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/**
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* @brief Halt the CPU
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*/
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void Halt();
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/**
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* @brief Check if interrupts are enabled
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*
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* @return true If InterruptsType::Check and interrupts are enabled, or if other InterruptsType were executed successfully
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* @return false If InterruptsType::Check and interrupts are disabled, or if other InterruptsType failed
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*/
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bool Interrupts(InterruptsType Type = Check);
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/**
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* @brief Get/Set the CPU's page table
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*
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* @param PT The new page table, if empty, the current page table will be returned
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* @return void* The current page table
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*/
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void *PageTable(void *PT = nullptr);
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namespace MemBar
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{
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static inline void Barrier()
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{
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/**
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* @brief Check if interrupts are enabled.
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*/
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Check,
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/**
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* @brief Enable interrupts.
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*/
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Enable,
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/**
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* @brief Disable interrupts.
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*/
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Disable
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};
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/**
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* @brief Get CPU vendor identifier.
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*
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* @return char* CPU Vendor ID.
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*/
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char *Vendor();
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/**
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* @brief Get CPU name.
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*
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* @return char* CPU Name.
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*/
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char *Name();
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/**
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* @brief Get CPU hypervisor vendor.
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*
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* @return char* Hypervisor vendor.
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*/
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char *Hypervisor();
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/**
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* @brief Pause the CPU
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*/
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void Pause();
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/**
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* @brief Halt the CPU
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*/
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void Halt();
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/**
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* @brief Check if interrupts are enabled
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*
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* @return true If InterruptsType::Check and interrupts are enabled, or if other InterruptsType were executed successfully
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* @return false If InterruptsType::Check and interrupts are disabled, or if other InterruptsType failed
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*/
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bool Interrupts(InterruptsType Type = Check);
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/**
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* @brief Get/Set the CPU's page table
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*
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* @param PT The new page table, if empty, the current page table will be returned
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* @return void* The current page table
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*/
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void *PageTable(void *PT = nullptr);
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namespace MemBar
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{
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static inline void Barrier()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("" ::
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: "memory");
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asmv("" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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static inline void Fence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("mfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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static inline void StoreFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("sfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishst" ::
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: "memory");
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#endif
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}
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static inline void LoadFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishld" ::
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: "memory");
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#endif
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}
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}
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namespace x86
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static inline void Fence()
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{
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lgdt (%0)"
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:
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: "r"(gdt));
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asmv("mfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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static inline void lidt(void *idt)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lidt (%0)"
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:
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: "r"(idt));
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#endif
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}
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static inline void ltr(uint16_t Segment)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("ltr %0"
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:
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: "r"(Segment));
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#endif
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}
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static inline void invlpg(void *Address)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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#endif
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}
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static inline void cpuid(uint32_t Function, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("cpuid"
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: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
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: "a"(Function));
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#endif
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}
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}
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static inline void StoreFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("sfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishst" ::
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: "memory");
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#endif
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}
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static inline void LoadFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishld" ::
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: "memory");
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#endif
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}
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}
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namespace x32
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{
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}
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namespace x64
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{
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typedef union
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{
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struct
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{
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/** @brief Carry Flag */
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uint64_t CF : 1;
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/** @brief Reserved */
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uint64_t always_one : 1;
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/** @brief Parity Flag */
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uint64_t PF : 1;
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/** @brief Reserved */
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uint64_t _reserved0 : 1;
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/** @brief Auxiliary Carry Flag */
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uint64_t AF : 1;
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/** @brief Reserved */
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uint64_t _reserved1 : 1;
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/** @brief Zero Flag */
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uint64_t ZF : 1;
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/** @brief Sign Flag */
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uint64_t SF : 1;
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/** @brief Trap Flag */
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uint64_t TF : 1;
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/** @brief Interrupt Enable Flag */
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uint64_t IF : 1;
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/** @brief Direction Flag */
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uint64_t DF : 1;
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/** @brief Overflow Flag */
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uint64_t OF : 1;
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/** @brief I/O Privilege Level */
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uint64_t IOPL : 2;
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/** @brief Nested Task */
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uint64_t NT : 1;
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/** @brief Reserved */
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uint64_t _reserved2 : 1;
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/** @brief Resume Flag */
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uint64_t RF : 1;
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/** @brief Virtual 8086 Mode */
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uint64_t VM : 1;
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/** @brief Alignment Check */
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uint64_t AC : 1;
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/** @brief Virtual Interrupt Flag */
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uint64_t VIF : 1;
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/** @brief Virtual Interrupt Pending */
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uint64_t VIP : 1;
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/** @brief ID Flag */
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uint64_t ID : 1;
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/** @brief Reserved */
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uint64_t _reserved3 : 10;
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};
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uint64_t raw;
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} RFLAGS;
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typedef struct _TrapFrame
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{
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// uint64_t gs; // General-purpose Segment
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// uint64_t fs; // General-purpose Segment
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// uint64_t es; // Extra Segment (used for string operations)
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uint64_t ds; // Data Segment
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uint64_t r15; // General purpose
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uint64_t r14; // General purpose
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uint64_t r13; // General purpose
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uint64_t r12; // General purpose
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uint64_t r11; // General purpose
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uint64_t r10; // General purpose
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uint64_t r9; // General purpose
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uint64_t r8; // General purpose
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uint64_t rbp; // Base Pointer (meant for stack frames)
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uint64_t rdi; // Destination index for string operations
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uint64_t rsi; // Source index for string operations
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uint64_t rdx; // Data (commonly extends the A register)
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uint64_t rcx; // Counter
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uint64_t rbx; // Base
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uint64_t rax; // Accumulator
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uint64_t int_num; // Interrupt Number
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uint64_t error_code; // Error code
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uint64_t rip; // Instruction Pointer
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uint64_t cs; // Code Segment
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RFLAGS rflags; // Register Flags
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uint64_t rsp; // Stack Pointer
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uint64_t ss; // Stack Segment
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} TrapFrame;
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__)
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asmv("lgdt (%0)"
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:
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: "r"(gdt));
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#endif
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}
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static inline void lidt(void *idt)
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{
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#if defined(__amd64__)
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asmv("lidt (%0)"
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:
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: "r"(idt));
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#endif
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}
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static inline void ltr(uint16_t Segment)
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{
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#if defined(__amd64__)
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asmv("ltr %0"
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:
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: "r"(Segment));
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#endif
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}
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static inline void invlpg(void *Address)
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{
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#if defined(__amd64__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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#endif
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}
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static inline void cpuid(uint32_t Function, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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#if defined(__amd64__)
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asmv("cpuid"
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: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
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: "a"(Function));
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#endif
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}
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}
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}
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#endif // !__FENNIX_KERNEL_CPU_H__
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11
include/interrupts.hpp
Normal file
11
include/interrupts.hpp
Normal file
@ -0,0 +1,11 @@
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#ifndef __FENNIX_KERNEL_INTERRUPTS_H__
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#define __FENNIX_KERNEL_INTERRUPTS_H__
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#include <types.h>
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namespace Interrupts
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{
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void Initialize();
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}
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#endif // !__FENNIX_KERNEL_INTERRUPTS_H__
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@ -45,6 +45,8 @@ typedef __builtin_va_list va_list;
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#define ALIGN_UP(x, align) ((__typeof__(x))(((uint64_t)(x) + ((align)-1)) & (~((align)-1))))
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#define ALIGN_DOWN(x, align) ((__typeof__(x))((x) & (~((align)-1))))
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#define offsetof(type, member) __builtin_offsetof(type, member)
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typedef __INT8_TYPE__ int8_t;
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typedef __INT16_TYPE__ int16_t;
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typedef __INT32_TYPE__ int32_t;
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