mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-07-11 15:29:18 +00:00
More tasking implementation
This commit is contained in:
@ -35,7 +35,7 @@ namespace APIC
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uint32_t APIC::Read(uint32_t Register)
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{
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debug("APIC::Read(%#lx)", Register);
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debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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@ -50,7 +50,7 @@ namespace APIC
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void APIC::Write(uint32_t Register, uint32_t Value)
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{
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if (Register != APIC_EOI)
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debug("APIC::Write(%#lx, %#lx)", Register, Value);
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debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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@ -58,8 +58,8 @@ namespace GlobalDescriptorTable
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tss[Core].InterruptStackTable[2] = (uint64_t)KernelAllocator.RequestPage();
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CPU::x64::ltr(GDT_TSS);
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asm volatile("mov %%rsp, %0"
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: "=r"(tss[Core].StackPointer[0]));
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asmv("mov %%rsp, %0"
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: "=r"(tss[Core].StackPointer[0]));
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trace("GDT_KERNEL_CODE: %#lx", GDT_KERNEL_CODE);
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trace("GDT_KERNEL_DATA: %#lx", GDT_KERNEL_DATA);
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@ -156,7 +156,8 @@ namespace InterruptDescriptorTable
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"jmp InterruptHandlerStub\n"); \
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}
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// ISR
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/* ISR */
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EXCEPTION_HANDLER(0x0);
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EXCEPTION_HANDLER(0x1);
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EXCEPTION_HANDLER(0x2);
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@ -189,7 +190,9 @@ namespace InterruptDescriptorTable
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EXCEPTION_HANDLER(0x1d);
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EXCEPTION_HANDLER(0x1e);
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EXCEPTION_HANDLER(0x1f);
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// IRQ
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/* IRQ */
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INTERRUPT_HANDLER(0x20)
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INTERRUPT_HANDLER(0x21)
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INTERRUPT_HANDLER(0x22)
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@ -207,7 +210,12 @@ namespace InterruptDescriptorTable
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INTERRUPT_HANDLER(0x2e)
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INTERRUPT_HANDLER(0x2f)
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INTERRUPT_HANDLER(0x30)
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/* Reserved by OS */
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__attribute__((naked, used, no_stack_protector)) void InterruptHandler_0x30() { asm("pushq $0\npushq $"
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"0x30"
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"\n"
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"jmp SchedulerInterruptStub\n"); }
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INTERRUPT_HANDLER(0x31)
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INTERRUPT_HANDLER(0x32)
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INTERRUPT_HANDLER(0x33)
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@ -221,6 +229,9 @@ namespace InterruptDescriptorTable
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INTERRUPT_HANDLER(0x3b)
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INTERRUPT_HANDLER(0x3c)
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INTERRUPT_HANDLER(0x3d)
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/* Free */
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INTERRUPT_HANDLER(0x3e)
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INTERRUPT_HANDLER(0x3f)
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INTERRUPT_HANDLER(0x40)
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@ -420,6 +431,8 @@ namespace InterruptDescriptorTable
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void Init(int Core)
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{
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/* ISR */
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SetEntry(0x0, InterruptHandler_0x0, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x1, InterruptHandler_0x1, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x2, InterruptHandler_0x2, FlagGate_32BIT_TRAP, 2, FlagGate_RING0, GDT_KERNEL_CODE);
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@ -452,7 +465,9 @@ namespace InterruptDescriptorTable
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SetEntry(0x1d, InterruptHandler_0x1d, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x1e, InterruptHandler_0x1e, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x1f, InterruptHandler_0x1f, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
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// IRQ
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/* IRQ */
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SetEntry(0x20, InterruptHandler_0x20, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x21, InterruptHandler_0x21, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x22, InterruptHandler_0x22, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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@ -470,6 +485,8 @@ namespace InterruptDescriptorTable
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SetEntry(0x2e, InterruptHandler_0x2e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x2f, InterruptHandler_0x2f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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/* Reserved by OS */
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SetEntry(0x30, InterruptHandler_0x30, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x31, InterruptHandler_0x31, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x32, InterruptHandler_0x32, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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@ -484,6 +501,9 @@ namespace InterruptDescriptorTable
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SetEntry(0x3b, InterruptHandler_0x3b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x3c, InterruptHandler_0x3c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x3d, InterruptHandler_0x3d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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/* Free */
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SetEntry(0x3e, InterruptHandler_0x3e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x3f, InterruptHandler_0x3f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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SetEntry(0x40, InterruptHandler_0x40, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
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@ -52,6 +52,8 @@ extern "C" void StartCPU()
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namespace SMP
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{
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int CPUCores = 0;
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void Initialize(void *madt)
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{
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if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) == 0)
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@ -67,6 +69,8 @@ namespace SMP
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else if (Config.Cores != 0)
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Cores = Config.Cores;
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CPUCores = Cores;
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for (uint16_t i = 0; i < Cores; i++)
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{
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debug("Initializing CPU %d", i);
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@ -87,8 +91,8 @@ namespace SMP
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POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
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POKE(volatile uint64_t, CORE) = i;
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asm volatile("sgdt [0x580]\n"
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"sidt [0x590]\n");
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asmv("sgdt [0x580]\n"
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"sidt [0x590]\n");
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POKE(volatile uint64_t, START_ADDR) = (uintptr_t)&StartCPU;
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@ -103,7 +107,7 @@ namespace SMP
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CPUEnabled = false;
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}
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else
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KPrint("CPU %d is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId);
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KPrint("\e058C19CPU \e8888FF%d \e058C19is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId);
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}
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}
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}
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@ -18,12 +18,12 @@ namespace APIC
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APIC_VER = 0x30, // Local APIC Version
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APIC_TPR = 0x80, // Task Priority
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APIC_APR = 0x90, // Arbitration Priority
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APIC_PPR = 0xa0, // Processor Priority
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APIC_EOI = 0xb0, // EOI
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APIC_RRD = 0xc0, // Remote Read
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APIC_LDR = 0xd0, // Logical Destination
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APIC_DFR = 0xe0, // Destination Format
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APIC_SVR = 0xf0, // Spurious Interrupt Vector
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APIC_PPR = 0xA0, // Processor Priority
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APIC_EOI = 0xB0, // EOI
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APIC_RRD = 0xC0, // Remote Read
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APIC_LDR = 0xD0, // Logical Destination
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APIC_DFR = 0xE0, // Destination Format
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APIC_SVR = 0xF0, // Spurious Interrupt Vector
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APIC_ISR = 0x100, // In-Service (8 registers)
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APIC_TMR = 0x180, // Trigger Mode (8 registers)
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APIC_IRR = 0x200, // Interrupt Request (8 registers)
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@ -38,7 +38,7 @@ namespace APIC
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APIC_ERROR = 0x370, // LVT Error
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APIC_TICR = 0x380, // Initial Count (for Timer)
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APIC_TCCR = 0x390, // Current Count (for Timer)
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APIC_TDCR = 0x3e0, // Divide Configuration (for Timer)
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APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
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};
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class APIC
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{
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