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More tasking implementation

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This commit is contained in:
Alex
2022-10-21 05:31:50 +03:00
parent 7477c55ccd
commit ebd0273a99
12 changed files with 347 additions and 84 deletions
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4
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -35,7 +35,7 @@ namespace APIC
uint32_t APIC::Read(uint32_t Register)
{
debug("APIC::Read(%#lx)", Register);
debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
if (x2APICSupported)
{
if (Register != APIC_ICRHI)
@ -50,7 +50,7 @@ namespace APIC
void APIC::Write(uint32_t Register, uint32_t Value)
{
if (Register != APIC_EOI)
debug("APIC::Write(%#lx, %#lx)", Register, Value);
debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
if (x2APICSupported)
{
if (Register != APIC_ICRHI)

4
Architecture/amd64/cpu/GlobalDescriptorTable.cpp
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@ -58,8 +58,8 @@ namespace GlobalDescriptorTable
tss[Core].InterruptStackTable[2] = (uint64_t)KernelAllocator.RequestPage();
CPU::x64::ltr(GDT_TSS);
asm volatile("mov %%rsp, %0"
: "=r"(tss[Core].StackPointer[0]));
asmv("mov %%rsp, %0"
: "=r"(tss[Core].StackPointer[0]));
trace("GDT_KERNEL_CODE: %#lx", GDT_KERNEL_CODE);
trace("GDT_KERNEL_DATA: %#lx", GDT_KERNEL_DATA);

28
Architecture/amd64/cpu/InterruptDescriptorTable.cpp
View File

@ -156,7 +156,8 @@ namespace InterruptDescriptorTable
"jmp InterruptHandlerStub\n"); \
}
// ISR
/* ISR */
EXCEPTION_HANDLER(0x0);
EXCEPTION_HANDLER(0x1);
EXCEPTION_HANDLER(0x2);
@ -189,7 +190,9 @@ namespace InterruptDescriptorTable
EXCEPTION_HANDLER(0x1d);
EXCEPTION_HANDLER(0x1e);
EXCEPTION_HANDLER(0x1f);
// IRQ
/* IRQ */
INTERRUPT_HANDLER(0x20)
INTERRUPT_HANDLER(0x21)
INTERRUPT_HANDLER(0x22)
@ -207,7 +210,12 @@ namespace InterruptDescriptorTable
INTERRUPT_HANDLER(0x2e)
INTERRUPT_HANDLER(0x2f)
INTERRUPT_HANDLER(0x30)
/* Reserved by OS */
__attribute__((naked, used, no_stack_protector)) void InterruptHandler_0x30() { asm("pushq $0\npushq $"
"0x30"
"\n"
"jmp SchedulerInterruptStub\n"); }
INTERRUPT_HANDLER(0x31)
INTERRUPT_HANDLER(0x32)
INTERRUPT_HANDLER(0x33)
@ -221,6 +229,9 @@ namespace InterruptDescriptorTable
INTERRUPT_HANDLER(0x3b)
INTERRUPT_HANDLER(0x3c)
INTERRUPT_HANDLER(0x3d)
/* Free */
INTERRUPT_HANDLER(0x3e)
INTERRUPT_HANDLER(0x3f)
INTERRUPT_HANDLER(0x40)
@ -420,6 +431,8 @@ namespace InterruptDescriptorTable
void Init(int Core)
{
/* ISR */
SetEntry(0x0, InterruptHandler_0x0, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x1, InterruptHandler_0x1, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x2, InterruptHandler_0x2, FlagGate_32BIT_TRAP, 2, FlagGate_RING0, GDT_KERNEL_CODE);
@ -452,7 +465,9 @@ namespace InterruptDescriptorTable
SetEntry(0x1d, InterruptHandler_0x1d, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x1e, InterruptHandler_0x1e, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x1f, InterruptHandler_0x1f, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
// IRQ
/* IRQ */
SetEntry(0x20, InterruptHandler_0x20, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x21, InterruptHandler_0x21, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x22, InterruptHandler_0x22, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
@ -470,6 +485,8 @@ namespace InterruptDescriptorTable
SetEntry(0x2e, InterruptHandler_0x2e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x2f, InterruptHandler_0x2f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
/* Reserved by OS */
SetEntry(0x30, InterruptHandler_0x30, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x31, InterruptHandler_0x31, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x32, InterruptHandler_0x32, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
@ -484,6 +501,9 @@ namespace InterruptDescriptorTable
SetEntry(0x3b, InterruptHandler_0x3b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x3c, InterruptHandler_0x3c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x3d, InterruptHandler_0x3d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
/* Free */
SetEntry(0x3e, InterruptHandler_0x3e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x3f, InterruptHandler_0x3f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
SetEntry(0x40, InterruptHandler_0x40, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);

10
Architecture/amd64/cpu/SymmetricMultiprocessing.cpp
View File

@ -52,6 +52,8 @@ extern "C" void StartCPU()
namespace SMP
{
int CPUCores = 0;
void Initialize(void *madt)
{
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) == 0)
@ -67,6 +69,8 @@ namespace SMP
else if (Config.Cores != 0)
Cores = Config.Cores;
CPUCores = Cores;
for (uint16_t i = 0; i < Cores; i++)
{
debug("Initializing CPU %d", i);
@ -87,8 +91,8 @@ namespace SMP
POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
POKE(volatile uint64_t, CORE) = i;
asm volatile("sgdt [0x580]\n"
"sidt [0x590]\n");
asmv("sgdt [0x580]\n"
"sidt [0x590]\n");
POKE(volatile uint64_t, START_ADDR) = (uintptr_t)&StartCPU;
@ -103,7 +107,7 @@ namespace SMP
CPUEnabled = false;
}
else
KPrint("CPU %d is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId);
KPrint("\e058C19CPU \e8888FF%d \e058C19is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId);
}
}
}

14
Architecture/amd64/cpu/apic.hpp
View File

@ -18,12 +18,12 @@ namespace APIC
APIC_VER = 0x30, // Local APIC Version
APIC_TPR = 0x80, // Task Priority
APIC_APR = 0x90, // Arbitration Priority
APIC_PPR = 0xa0, // Processor Priority
APIC_EOI = 0xb0, // EOI
APIC_RRD = 0xc0, // Remote Read
APIC_LDR = 0xd0, // Logical Destination
APIC_DFR = 0xe0, // Destination Format
APIC_SVR = 0xf0, // Spurious Interrupt Vector
APIC_PPR = 0xA0, // Processor Priority
APIC_EOI = 0xB0, // EOI
APIC_RRD = 0xC0, // Remote Read
APIC_LDR = 0xD0, // Logical Destination
APIC_DFR = 0xE0, // Destination Format
APIC_SVR = 0xF0, // Spurious Interrupt Vector
APIC_ISR = 0x100, // In-Service (8 registers)
APIC_TMR = 0x180, // Trigger Mode (8 registers)
APIC_IRR = 0x200, // Interrupt Request (8 registers)
@ -38,7 +38,7 @@ namespace APIC
APIC_ERROR = 0x370, // LVT Error
APIC_TICR = 0x380, // Initial Count (for Timer)
APIC_TCCR = 0x390, // Current Count (for Timer)
APIC_TDCR = 0x3e0, // Divide Configuration (for Timer)
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
};
class APIC
{