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https://github.com/Fennix-Project/Kernel.git
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Fixed tasking SSE
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Alex
parent
5da3b3ae6c
commit
e53bc14240
GPG Key ID:
EACC3AD603BAB4DD
@ -1,11 +0,0 @@
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[bits 64]
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[global _amd64_fxsave]
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_amd64_fxsave:
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fxsave [rdi]
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ret
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[global _amd64_fxrstor]
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_amd64_fxrstor:
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fxrstor [rdi]
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ret
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@ -1,11 +0,0 @@
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[bits 64]
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[global _i386_fxsave]
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_i386_fxsave:
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fxsave [edi]
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ret
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[global _i386_fxrstor]
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_i386_fxrstor:
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fxrstor [edi]
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ret
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27
Core/CPU.cpp
27
Core/CPU.cpp
@ -209,30 +209,35 @@ namespace CPU
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debug("Enabling UMIP, SMEP & SMAP support...");
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x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
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if (rdx & x64::CPUID_FEAT_RDX_UMIP)
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if (rdx & x64::CPUID_FEAT_RDX_UMIP) // https://en.wikipedia.org/wiki/Control_register
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{
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if (!BSP)
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KPrint("UMIP is supported.");
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fixme("Not going to enable UMIP.");
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cr4.UMIP = 1;
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debug("UMIP is supported.");
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// cr4.UMIP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMEP)
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if (rdx & x64::CPUID_FEAT_RDX_SMEP) // https://en.wikipedia.org/wiki/Control_register#SMEP
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// https://web.archive.org/web/20160312223150/http://ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf
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{
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if (!BSP)
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KPrint("SMEP is supported.");
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fixme("Not going to enable SMEP.");
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cr4.SMEP = 1;
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debug("SMEP is supported.");
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// cr4.SMEP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMAP)
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if (rdx & x64::CPUID_FEAT_RDX_SMAP) // https://en.wikipedia.org/wiki/Supervisor_Mode_Access_Prevention
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{
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if (!BSP)
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KPrint("SMAP is supported.");
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fixme("Not going to enable SMAP.");
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cr4.SMAP = 1;
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debug("SMAP is supported.");
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// cr4.SMAP = 1;
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}
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) == 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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{
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debug("Writing CR4...");
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x64::writecr4(cr4);
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debug("Wrote CR4.");
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}
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else
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{
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if (!BSP)
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4
Makefile
4
Makefile
@ -61,8 +61,8 @@ CFLAGS := \
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ifeq ($(OSARCH), amd64)
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CFLAGS += -fno-pic -fno-pie -mno-80387 -mno-mmx -mno-3dnow \
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-mno-red-zone -march=x86-64 -pipe \
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CFLAGS += -fno-pic -fno-pie \
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-mno-red-zone -march=x86-64 -pipe \
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-mcmodel=kernel -msoft-float -fno-builtin
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CFLAG_STACK_PROTECTOR := -fstack-protector-all
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LDFLAGS += -TArchitecture/amd64/linker.ld \
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@ -379,6 +379,10 @@ namespace Tasking
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tcb->Info.SleepUntil = 0;
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schedbg("Thread \"%s\"(%d) woke up.", tcb->Name, tcb->ID);
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}
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else
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{
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schedbg("Thread \"%s\"(%d) is not ready to wake up. (SleepUntil: %d, Counter: %d)", tcb->Name, tcb->ID, tcb->Info.SleepUntil, TimeManager->GetCounter());
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}
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}
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}
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}
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@ -433,7 +437,7 @@ namespace Tasking
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{
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// Save current process and thread registries, gs, fs, fpu, etc...
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CurrentCPU->CurrentThread->Registers = *Frame;
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CPU::x64::fxsave(CurrentCPU->CurrentThread->FXRegion);
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CPU::x64::fxsave(CurrentCPU->CurrentThread->FPU);
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CurrentCPU->CurrentThread->GSBase = CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE);
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CurrentCPU->CurrentThread->FSBase = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
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@ -548,7 +552,7 @@ namespace Tasking
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// Not sure if this is needed, but it's better to be safe than sorry.
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asmv("movq %cr3, %rax");
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asmv("movq %rax, %cr3");
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CPU::x64::fxrstor(CurrentCPU->CurrentThread->FXRegion);
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CPU::x64::fxrstor(CurrentCPU->CurrentThread->FPU);
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CPU::x64::wrmsr(CPU::x64::MSR_GS_BASE, CurrentCPU->CurrentThread->GSBase);
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CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, CurrentCPU->CurrentThread->FSBase);
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@ -729,10 +733,11 @@ namespace Tasking
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void Task::Sleep(uint64_t Milliseconds)
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{
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SmartCriticalSection(SchedulerLock);
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SmartCriticalSection(TaskingLock);
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TCB *thread = this->GetCurrentThread();
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thread->Status = TaskStatus::Sleeping;
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thread->Info.SleepUntil = TimeManager->CalculateTarget(Milliseconds);
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schedbg("Thread \"%s\"(%d) is going to sleep until %llu", thread->Name, thread->ID, thread->Info.SleepUntil);
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OneShot(1);
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}
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@ -773,6 +778,27 @@ namespace Tasking
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Thread->Offset = Offset;
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Thread->ExitCode = 0xdead;
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Thread->Status = TaskStatus::Ready;
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Thread->Memory = new Memory::MemMgr(Parent->PageTable);
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Thread->FPU = (FXState *)Thread->Memory->RequestPages(TO_PAGES(sizeof(FXState)));
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memset(Thread->FPU, 0, FROM_PAGES(TO_PAGES(sizeof(FXState))));
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// TODO: Is really a good idea to use the FPU in kernel mode?
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Thread->FPU->mxcsr = 0b0001111110000000;
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Thread->FPU->mxcsrmask = 0b1111111110111111;
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Thread->FPU->fcw = 0b0000001100111111;
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CPU::x64::fxrstor(Thread->FPU);
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// uint16_t FCW = 0b1100111111;
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// asmv("fldcw %0"
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// :
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// : "m"(FCW)
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// : "memory");
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// uint32_t MXCSR = 0b1111110000000;
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// asmv("ldmxcsr %0"
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// :
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// : "m"(MXCSR)
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// : "memory");
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// CPU::x64::fxsave(Thread->FPU);
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#if defined(__amd64__)
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memset(&Thread->Registers, 0, sizeof(CPU::x64::TrapFrame)); // Just in case
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@ -808,7 +834,6 @@ namespace Tasking
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case TaskTrustLevel::User:
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{
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Thread->Stack = new Memory::StackGuard(true, Parent->PageTable);
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Thread->Memory = new Memory::MemMgr(Parent->PageTable);
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#if defined(__amd64__)
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SecurityManager.TrustToken(Thread->Security.UniqueToken, TokenTrustLevel::Untrusted);
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Thread->GSBase = 0;
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@ -823,6 +848,8 @@ namespace Tasking
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Thread->Registers.rflags.ID = 1;
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Thread->Registers.rsp = ((uintptr_t)Thread->Stack->GetStackTop());
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#pragma region
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size_t ArgvSize = 0;
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if (argv)
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while (argv[ArgvSize] != nullptr)
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@ -942,6 +969,8 @@ namespace Tasking
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Thread->Registers.rcx = (uintptr_t)EnvpSize; // envc
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Thread->Registers.rdx = (uintptr_t)(Thread->Registers.rsp + 8 + (8 * ArgvSize) + 8); // envp
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#pragma endregion
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/* We need to leave the libc's crt to make a syscall when the Thread is exited or we are going to get GPF or PF exception. */
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Memory::Virtual uva = Memory::Virtual(Parent->PageTable);
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@ -5,11 +5,6 @@
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#include <cstring>
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extern "C" void _amd64_fxsave(char *Buffer);
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extern "C" void _amd64_fxrstor(char *Buffer);
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extern "C" void _i386_fxsave(char *Buffer);
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extern "C" void _i386_fxrstor(char *Buffer);
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#define x86_CPUID_VENDOR_OLDAMD "AMDisbetter!" /* Early engineering samples of AMD K5 processor */
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#define x86_CPUID_VENDOR_AMD "AuthenticAMD"
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#define x86_CPUID_VENDOR_INTEL "GenuineIntel"
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@ -3404,31 +3399,29 @@ namespace CPU
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#endif
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}
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SafeFunction static inline void fxsave(char *FXSaveArea)
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SafeFunction static inline void fxsave(void *FXSaveArea)
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{
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#if defined(__amd64__)
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if (!FXSaveArea || FXSaveArea >= (char *)0xfffffffffffff000)
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return;
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_amd64_fxsave(FXSaveArea);
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// asmv("fxsaveq (%0)"
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// :
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// : "r"(FXSaveArea)
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// : "memory");
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asmv("fxsaveq (%0)"
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:
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: "r"(FXSaveArea)
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: "memory");
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#endif
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}
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SafeFunction static inline void fxrstor(char *FXRstorArea)
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SafeFunction static inline void fxrstor(void *FXRstorArea)
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{
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#if defined(__amd64__)
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if (!FXRstorArea || FXRstorArea >= (char *)0xfffffffffffff000)
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return;
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_amd64_fxrstor(FXRstorArea);
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// asmv("fxrstorq (%0)"
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// :
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// : "r"(FXRstorArea)
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// : "memory");
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asmv("fxrstorq (%0)"
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:
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: "r"(FXRstorArea)
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: "memory");
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#endif
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}
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@ -57,6 +57,32 @@ namespace Tasking
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Terminated
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};
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struct FXState
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{
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/** @brief FPU control word */
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uint16_t fcw;
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/** @brief FPU status word */
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uint16_t fsw;
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/** @brief FPU tag words */
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uint8_t ftw;
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/** @brief Reserved (zero) */
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uint8_t Reserved;
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/** @brief FPU opcode */
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uint16_t fop;
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/** @brief PFU instruction pointer */
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uint64_t rip;
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/** @brief FPU data pointer */
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uint64_t rdp;
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/** @brief SSE control register */
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uint32_t mxcsr;
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/** @brief SSE control register mask */
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uint32_t mxcsrmask;
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/** @brief FPU registers (last 6 bytes reserved) */
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uint8_t st[8][16];
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/** @brief XMM registers */
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uint8_t xmm[16][16];
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} __attribute__((packed));
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struct TaskSecurity
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{
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TaskTrustLevel TrustLevel;
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@ -104,7 +130,7 @@ namespace Tasking
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uintptr_t IPHistory[128];
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TaskSecurity Security;
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TaskInfo Info;
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char FXRegion[512] __attribute__((aligned(16)));
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FXState *FPU;
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void Rename(const char *name)
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{
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