mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-07-11 07:19:20 +00:00
Kernel now compiles on x32
This commit is contained in:
Alex
@ -65,6 +65,7 @@ typedef struct
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#if defined(__amd64__)
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Elf64_auxv_t archaux;
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#elif defined(__i386__)
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Elf32_auxv_t archaux;
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#elif defined(__aarch64__)
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#endif
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} AuxiliaryVector;
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294
include/cpu.hpp
294
include/cpu.hpp
@ -260,6 +260,282 @@ namespace CPU
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namespace x32
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{
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typedef union
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{
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struct
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{
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/** @brief Carry Flag */
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uint32_t CF : 1;
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/** @brief Reserved */
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uint32_t AlwaysOne : 1;
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/** @brief Parity Flag */
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uint32_t PF : 1;
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/** @brief Reserved */
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uint32_t Reserved0 : 1;
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/** @brief Auxiliary Carry Flag */
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uint32_t AF : 1;
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/** @brief Reserved */
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uint32_t Reserved1 : 1;
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/** @brief Zero Flag */
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uint32_t ZF : 1;
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/** @brief Sign Flag */
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uint32_t SF : 1;
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/** @brief Trap Flag */
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uint32_t TF : 1;
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/** @brief Interrupt Enable Flag */
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uint32_t IF : 1;
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/** @brief Direction Flag */
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uint32_t DF : 1;
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/** @brief Overflow Flag */
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uint32_t OF : 1;
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/** @brief I/O Privilege Level */
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uint32_t IOPL : 2;
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/** @brief Nested Task */
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uint32_t NT : 1;
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/** @brief Reserved */
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uint32_t Reserved2 : 1;
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/** @brief Resume Flag */
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uint32_t RF : 1;
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/** @brief Virtual 8086 Mode */
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uint32_t VM : 1;
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/** @brief Alignment Check */
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uint32_t AC : 1;
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/** @brief Virtual Interrupt Flag */
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uint32_t VIF : 1;
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/** @brief Virtual Interrupt Pending */
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uint32_t VIP : 1;
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/** @brief ID Flag */
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uint32_t ID : 1;
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};
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uint32_t raw;
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} EFLAGS;
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typedef struct TrapFrame
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{
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// uint32_t gs; // General-purpose Segment
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// uint32_t fs; // General-purpose Segment
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// uint32_t es; // Extra Segment (used for string operations)
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uint32_t ds; // Data Segment
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uint32_t ebp; // Base Pointer (meant for stack frames)
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uint32_t edi; // Destination index for string operations
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uint32_t esi; // Source index for string operations
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uint32_t edx; // Data (commonly extends the A register)
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uint32_t ecx; // Counter
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uint32_t ebx; // Base
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uint32_t eax; // Accumulator
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uint32_t InterruptNumber; // Interrupt Number
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uint32_t ErrorCode; // Error code
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uint32_t eip; // Instruction Pointer
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uint32_t cs; // Code Segment
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EFLAGS eflags; // Register Flags
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uint32_t esp; // Stack Pointer
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uint32_t ss; // Stack Segment
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} TrapFrame;
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typedef union CR0
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{
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struct
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{
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/** @brief Protection Enable */
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uint32_t PE : 1;
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/** @brief Monitor Coprocessor */
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uint32_t MP : 1;
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/** @brief Emulation */
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uint32_t EM : 1;
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/** @brief Task Switched */
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uint32_t TS : 1;
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/** @brief Extension Type */
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uint32_t ET : 1;
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/** @brief Numeric Error */
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uint32_t NE : 1;
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/** @brief Reserved */
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uint32_t Reserved0 : 10;
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/** @brief Write Protect */
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uint32_t WP : 1;
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/** @brief Reserved */
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uint32_t Reserved1 : 1;
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/** @brief Alignment Mask */
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uint32_t AM : 1;
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/** @brief Reserved */
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uint32_t Reserved2 : 10;
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/** @brief Not Write-through */
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uint32_t NW : 1;
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/** @brief Cache Disable */
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uint32_t CD : 1;
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/** @brief Paging */
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uint32_t PG : 1;
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};
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uint32_t raw;
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} CR0;
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typedef union CR2
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{
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struct
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{
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/** @brief Page Fault Linear Address */
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uint32_t PFLA;
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};
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uint32_t raw;
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} CR2;
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typedef union CR3
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{
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struct
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{
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/** @brief Not used if bit 17 of CR4 is 1 */
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uint32_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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uint32_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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uint32_t PDBR;
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};
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uint32_t raw;
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} CR3;
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typedef union CR4
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{
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struct
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{
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/** @brief Virtual-8086 Mode Extensions */
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uint32_t VME : 1;
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/** @brief Protected-Mode Virtual Interrupts */
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uint32_t PVI : 1;
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/** @brief Time Stamp Disable */
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uint32_t TSD : 1;
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/** @brief Debugging Extensions */
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uint32_t DE : 1;
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/** @brief Page Size Extensions */
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uint32_t PSE : 1;
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/** @brief Physical Address Extension */
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uint32_t PAE : 1;
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/** @brief Machine Check Enable */
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uint32_t MCE : 1;
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/** @brief Page Global Enable */
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uint32_t PGE : 1;
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/** @brief Performance Monitoring Counter */
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uint32_t PCE : 1;
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/** @brief Operating System Support */
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uint32_t OSFXSR : 1;
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/** @brief Operating System Support */
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uint32_t OSXMMEXCPT : 1;
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/** @brief User-Mode Instruction Prevention */
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uint32_t UMIP : 1;
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/** @brief Linear Address 57bit */
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uint32_t LA57 : 1;
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/** @brief VMX Enable */
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uint32_t VMXE : 1;
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/** @brief SMX Enable */
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uint32_t SMXE : 1;
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/** @brief Reserved */
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uint32_t Reserved0 : 1;
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/** @brief FSGSBASE Enable */
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uint32_t FSGSBASE : 1;
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/** @brief PCID Enable */
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uint32_t PCIDE : 1;
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/** @brief XSAVE and Processor Extended States Enable */
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uint32_t OSXSAVE : 1;
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/** @brief Reserved */
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uint32_t Reserved1 : 1;
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/** @brief SMEP Enable */
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uint32_t SMEP : 1;
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/** @brief SMAP Enable */
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uint32_t SMAP : 1;
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/** @brief Protection-Key Enable */
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uint32_t PKE : 1;
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/** @brief Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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/* @brief Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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};
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uint32_t raw;
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} CR4;
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typedef union CR8
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{
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struct
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{
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/** @brief Task Priority Level */
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uint32_t TPL : 1;
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};
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uint32_t raw;
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} CR8;
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/* TODO: Does EFER exists in x32? */
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typedef union EFER
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{
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struct
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{
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/** @brief Enable syscall & sysret instructions in 64-bit mode. */
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uint32_t SCE : 1;
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/** @brief Reserved */
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uint32_t Reserved0 : 7;
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/** @brief Enable long mode. */
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uint32_t LME : 1;
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/** @brief Reserved */
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uint32_t Reserved1 : 1;
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/** @brief Indicates long. */
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uint32_t LMA : 1;
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/** @brief Enable No-Execute Bit */
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uint32_t NXE : 1;
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/** @brief Enable Secure Virtual Machine */
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uint32_t SVME : 1;
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/** @brief Enable Long Mode Segment Limit */
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uint32_t LMSLE : 1;
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/** @brief Enable Fast FXSAVE/FXRSTOR */
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uint32_t FFXSR : 1;
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/** @brief Enable Translation Cache Extension */
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uint32_t TCE : 1;
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/** @brief Reserved */
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uint32_t Reserved2 : 32;
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};
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uint32_t raw;
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} __attribute__((packed)) EFER;
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// ! TODO: UNTESTED!
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typedef union DR7
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{
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struct
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{
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/** @brief Local DR0 Breakpoint (0) */
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uint32_t LocalDR0 : 1;
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/** @brief Global DR0 Breakpoint (1) */
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uint32_t GlobalDR0 : 1;
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/** @brief Local DR1 Breakpoint (2) */
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uint32_t LocalDR1 : 1;
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/** @brief Global DR1 Breakpoint (3) */
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uint32_t GlobalDR1 : 1;
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/** @brief Local DR2 Breakpoint (4) */
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uint32_t LocalDR2 : 1;
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/** @brief Global DR2 Breakpoint (5) */
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uint32_t GlobalDR2 : 1;
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/** @brief Local DR3 Breakpoint (6) */
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uint32_t LocalDR3 : 1;
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/** @brief Global DR3 Breakpoint (7) */
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uint32_t GlobalDR3 : 1;
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/** @brief Reserved [7 - (16-17)] */
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uint32_t Reserved : 9;
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/** @brief Conditions for DR0 (16-17) */
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uint32_t ConditionsDR0 : 1;
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/** @brief Size of DR0 Breakpoint (18-19) */
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uint32_t SizeDR0 : 1;
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/** @brief Conditions for DR1 (20-21) */
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uint32_t ConditionsDR1 : 1;
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/** @brief Size of DR1 Breakpoint (22-23) */
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uint32_t SizeDR1 : 1;
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/** @brief Conditions for DR2 (24-25) */
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uint32_t ConditionsDR2 : 1;
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/** @brief Size of DR2 Breakpoint (26-27) */
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uint32_t SizeDR2 : 1;
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/** @brief Conditions for DR3 (28-29) */
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uint32_t ConditionsDR3 : 1;
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/** @brief Size of DR3 Breakpoint (30-31) */
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uint32_t SizeDR3 : 1;
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};
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uint32_t raw;
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} DR7;
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/**
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* @brief CPUID
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*
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@ -275,6 +551,16 @@ namespace CPU
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asmv("cpuid"
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: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
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: "a"(Function));
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#endif
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}
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__no_stack_protector static inline void invlpg(void *Address)
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{
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#if defined(__i386__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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#endif
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}
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}
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@ -1167,7 +1453,7 @@ namespace CPU
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uint64_t AM : 1;
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/** @brief Reserved */
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uint64_t Reserved2 : 10;
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/** @brief Mot Write-through */
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/** @brief Not Write-through */
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uint64_t NW : 1;
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/** @brief Cache Disable */
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uint64_t CD : 1;
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@ -1251,8 +1537,12 @@ namespace CPU
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uint64_t SMAP : 1;
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/** @brief Protection-Key Enable */
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uint64_t PKE : 1;
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/** @brief Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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/* @brief Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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/** @brief Reserved */
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uint64_t Reserved2 : 9;
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uint64_t Reserved2 : 7; // TODO: This could be wrong
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};
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uint64_t raw;
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} CR4;
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@ -10,7 +10,8 @@ namespace Interrupts
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/* APIC::APIC */ extern void *apic[256]; // MAX_CPU
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/* APIC::Timer */ extern void *apicTimer[256]; // MAX_CPU
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#elif defined(__i386__)
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extern void *apic[256]; // MAX_CPU
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/* APIC::APIC */ extern void *apic[256]; // MAX_CPU
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/* APIC::Timer */ extern void *apicTimer[256]; // MAX_CPU
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#elif defined(__aarch64__)
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#endif
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void Initialize(int Core);
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