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Various QoL changes

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This commit is contained in:
Alex
2023-09-03 19:24:14 +03:00
parent 4abf69f597
commit c5c76d3f9d
8 changed files with 138 additions and 167 deletions
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2
Architecture/i386/Bootstrap/Multiboot/2/Multiboot.cpp
View File

@@ -197,7 +197,7 @@ EXTERNC void multiboot_main(uintptr_t Magic, uintptr_t Info)
}
}
debug("Framebuffer %d: %dx%d %d bpp", fb_count, fb->common.framebuffer_width, fb->common.framebuffer_height, fb->common.framebuffer_bpp);
debug("More info:\nAddress: %p\nPitch: %lld\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
debug("More info:\nAddress: %p\nPitch: %d\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
fb->common.framebuffer_addr, fb->common.framebuffer_pitch, fb->common.framebuffer_type,
fb->framebuffer_red_mask_size, fb->framebuffer_red_field_position, fb->framebuffer_green_mask_size,
fb->framebuffer_green_field_position, fb->framebuffer_blue_mask_size, fb->framebuffer_blue_field_position);

26
Architecture/i386/cpu/SymmetricMultiprocessing.cpp
View File

@@ -41,20 +41,34 @@ enum SMPTrampolineAddress
std::atomic_bool CPUEnabled = false;
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
static __aligned(0x1000) CPUData CPUs[MAX_CPU] = {0};
static __aligned(PAGE_SIZE) CPUData CPUs[MAX_CPU] = {0};
SafeFunction CPUData *GetCPU(long id) { return &CPUs[id]; }
SafeFunction CPUData *GetCurrentCPU()
{
uint64_t ret = 0;
if (!(&CPUs[ret])->IsActive)
if (unlikely(!Interrupts::apic[0]))
return &CPUs[0]; /* No APIC means we are on the BSP. */
APIC::APIC *apic = (APIC::APIC *)Interrupts::apic[0];
int CoreID = 0;
if (CPUEnabled.load(std::memory_order_acquire) == true)
{
// error("CPU %d is not active!", ret); FIXME
if (apic->x2APIC)
CoreID = int(CPU::x32::rdmsr(CPU::x32::MSR_X2APIC_APICID));
else
CoreID = apic->Read(APIC::APIC_ID) >> 24;
}
if (unlikely((&CPUs[CoreID])->IsActive != true))
{
error("CPU %d is not active!", CoreID);
assert((&CPUs[0])->IsActive == true); /* We can't continue without the BSP. */
return &CPUs[0];
}
assert((&CPUs[ret])->Checksum == CPU_DATA_CHECKSUM);
return &CPUs[ret];
assert((&CPUs[CoreID])->Checksum == CPU_DATA_CHECKSUM); /* This should never happen. */
return &CPUs[CoreID];
}
namespace SMP

2
Architecture/i386/cpu/apic.hpp
View File

@@ -319,6 +319,8 @@ namespace APIC
uint64_t APICBaseAddress = 0;
public:
decltype(x2APICSupported) &x2APIC = x2APICSupported;
uint32_t Read(uint32_t Register);
void Write(uint32_t Register, uint32_t Value);
void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);