mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-07-17 02:01:44 +00:00
Fix 32-bit compilation
This commit is contained in:
Alex
@@ -0,0 +1,411 @@
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "apic.hpp"
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#include <memory.hpp>
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#include <uart.hpp>
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#include <lock.hpp>
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#include <cpu.hpp>
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#include <smp.hpp>
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#include <io.h>
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#include "../../../kernel.h"
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#include "../acpi.hpp"
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NewLock(APICLock);
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using namespace CPU::x32;
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using namespace CPU::x86;
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/*
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In constructor ‘APIC::APIC::APIC(int)’:
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warning: left shift count >= width of type
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| APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
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| ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
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*/
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#pragma GCC diagnostic ignored "-Wshift-count-overflow"
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namespace APIC
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{
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// headache
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// https://www.amd.com/system/files/TechDocs/24593.pdf
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// https://www.naic.edu/~phil/software/intel/318148.pdf
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uint32_t APIC::Read(uint32_t Register)
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{
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#ifdef DEBUG
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if (Register != APIC_ICRLO &&
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Register != APIC_ICRHI &&
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Register != APIC_ID)
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debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
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#endif
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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return s_cst(uint32_t, rdmsr((Register >> 4) + 0x800));
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else
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return s_cst(uint32_t, rdmsr(0x30 + 0x800));
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}
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else
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{
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
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CPU::MemBar::Barrier();
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return ret;
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}
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}
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void APIC::Write(uint32_t Register, uint32_t Value)
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{
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#ifdef DEBUG
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if (Register != APIC_EOI &&
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Register != APIC_TDCR &&
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Register != APIC_TIMER &&
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Register != APIC_TICR &&
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Register != APIC_ICRLO &&
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Register != APIC_ICRHI)
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debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
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#endif
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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wrmsr((Register >> 4) + 0x800, Value);
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else
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wrmsr(MSR_X2APIC_ICR, Value);
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}
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else
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{
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
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CPU::MemBar::Barrier();
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}
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}
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void APIC::IOWrite(uint64_t Base, uint32_t Register, uint32_t Value)
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{
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debug("APIC::IOWrite(%#lx, %#lx, %#lx)", Base, Register, Value);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base + 16))) = Value;
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CPU::MemBar::Barrier();
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}
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uint32_t APIC::IORead(uint64_t Base, uint32_t Register)
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{
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debug("APIC::IORead(%#lx, %#lx)", Base, Register);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)(((uintptr_t)Base + 16)));
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CPU::MemBar::Barrier();
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return ret;
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}
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void APIC::EOI() { this->Write(APIC_EOI, 0); }
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void APIC::WaitForIPI()
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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do
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{
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icr.raw = this->Read(APIC_ICRLO);
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CPU::Pause();
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} while (icr.DeliveryStatus != Idle);
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}
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void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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else
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{
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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}
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void APIC::SendInitIPI(uint8_t CPU)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.DeliveryMode = INIT;
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icr.Level = Assert;
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wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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else
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.DeliveryMode = INIT;
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icr.Level = Assert;
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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}
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void APIC::SendStartupIPI(uint8_t CPU, uint64_t StartupAddress)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.Vector = s_cst(uint8_t, StartupAddress >> 12);
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icr.DeliveryMode = Startup;
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icr.Level = Assert;
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wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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else
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.Vector = s_cst(uint8_t, StartupAddress >> 12);
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icr.DeliveryMode = Startup;
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icr.Level = Assert;
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
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this->WaitForIPI();
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}
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}
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uint32_t APIC::IOGetMaxRedirect(uint32_t APICID)
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{
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uint32_t TableAddress = (this->IORead((((ACPI::MADT *)PowerManager->GetMADT())->ioapic[APICID]->Address), GetIOAPICVersion));
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return ((IOAPICVersion *)&TableAddress)->MaximumRedirectionEntry;
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}
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void APIC::RawRedirectIRQ(uint16_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status)
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{
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uint64_t Value = Vector;
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int64_t IOAPICTarget = -1;
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for (uint64_t i = 0; ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)] != 0; i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)]->GSIBase <= GSI)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)]->GSIBase + IOGetMaxRedirect(s_cst(uint32_t, i)) > GSI)
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{
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IOAPICTarget = i;
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break;
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}
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if (IOAPICTarget == -1)
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{
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error("No ISO table found for I/O APIC");
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return;
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}
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// TODO: IOAPICRedirectEntry Entry = {.raw = 0};
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if (Flags & ActiveHighLow)
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Value |= (1 << 13);
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if (Flags & EdgeLevel)
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Value |= (1 << 15);
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if (!Status)
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Value |= (1 << 16);
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Value |= (((uintptr_t)CPU) << 56);
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uint32_t IORegister = (GSI - ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->GSIBase) * 2 + 16;
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->Address,
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IORegister, (uint32_t)Value);
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->Address,
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IORegister + 1, (uint32_t)(Value >> 32));
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}
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void APIC::RedirectIRQ(int CPU, uint16_t IRQ, int Status)
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{
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for (uint64_t i = 0; i < ((ACPI::MADT *)PowerManager->GetMADT())->iso.size(); i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource == IRQ)
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{
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debug("[ISO %d] Mapping to source IRQ%#d GSI:%#lx on CPU %d",
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i, ((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource,
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((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->GSI,
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CPU);
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this->RawRedirectIRQ(((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource + 0x20,
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((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->GSI,
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((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->Flags,
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CPU, Status);
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return;
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}
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debug("Mapping IRQ%d on CPU %d", IRQ, CPU);
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this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
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}
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void APIC::RedirectIRQs(int CPU)
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{
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SmartCriticalSection(APICLock);
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debug("Redirecting IRQs...");
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for (uint8_t i = 0; i < 16; i++)
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this->RedirectIRQ(CPU, i, 1);
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debug("Redirecting IRQs completed.");
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}
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APIC::APIC(int Core)
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{
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SmartCriticalSection(APICLock);
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APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
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uint64_t BaseLow = BaseStruct.ApicBaseLo;
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uint64_t BaseHigh = BaseStruct.ApicBaseHi;
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this->APICBaseAddress = BaseLow << 12u | BaseHigh << 32u;
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trace("APIC Address: %#lx", this->APICBaseAddress);
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Memory::Virtual().Map((void *)this->APICBaseAddress, (void *)this->APICBaseAddress, Memory::PTFlag::RW | Memory::PTFlag::PCD);
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bool x2APICSupported = false;
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid;
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cpuid.Get();
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if (cpuid.ECX.x2APIC)
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{
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// x2APICSupported = cpuid.ECX.x2APIC;
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fixme("x2APIC is supported");
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}
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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CPU::x86::Intel::CPUID0x00000001 cpuid;
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cpuid.Get();
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if (cpuid.ECX.x2APIC)
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{
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// x2APICSupported = cpuid.ECX.x2APIC;
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fixme("x2APIC is supported");
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}
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}
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if (x2APICSupported)
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{
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this->x2APICSupported = true;
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wrmsr(MSR_APIC_BASE, (rdmsr(MSR_APIC_BASE) | (1 << 11)) & ~(1 << 10));
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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else
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{
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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this->Write(APIC_TPR, 0x0);
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// this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
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if (!this->x2APICSupported)
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{
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this->Write(APIC_DFR, 0xF0000000);
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this->Write(APIC_LDR, this->Read(APIC_ID));
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}
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ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
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for (size_t i = 0; i < madt->nmi.size(); i++)
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{
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if (madt->nmi[std::size_t(i)]->processor != 0xFF && Core != madt->nmi[std::size_t(i)]->processor)
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return;
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uint32_t nmi = 0x402;
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if (madt->nmi[std::size_t(i)]->flags & 2)
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nmi |= 1 << 13;
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if (madt->nmi[std::size_t(i)]->flags & 8)
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nmi |= 1 << 15;
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if (madt->nmi[std::size_t(i)]->lint == 0)
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this->Write(APIC_LINT0, nmi);
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else if (madt->nmi[std::size_t(i)]->lint == 1)
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this->Write(APIC_LINT1, nmi);
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}
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// Setup the spurrious interrupt vector
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Spurious Spurious = {.raw = this->Read(APIC_SVR)};
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Spurious.Vector = IRQ223; // TODO: Should I map the IRQ to something?
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Spurious.Software = 1;
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this->Write(APIC_SVR, s_cst(uint32_t, Spurious.raw));
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static int once = 0;
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if (!once++)
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{
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// Disable PIT
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outb(0x43, 0x28);
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outb(0x40, 0x0);
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// Disable PIC
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outb(0x21, 0xFF);
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outb(0xA1, 0xFF);
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}
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}
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APIC::~APIC() {}
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void Timer::OnInterruptReceived(TrapFrame *Frame) { UNUSED(Frame); }
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void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
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{
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SmartCriticalSection(APICLock);
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LVTTimer timer = {.raw = 0};
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timer.Vector = s_cst(uint8_t, Vector);
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timer.TimerMode = 0;
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if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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this->lapic->Write(APIC_TDCR, DivideBy128);
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else
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this->lapic->Write(APIC_TDCR, DivideBy16);
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this->lapic->Write(APIC_TICR, s_cst(uint32_t, Ticks * Miliseconds));
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this->lapic->Write(APIC_TIMER, s_cst(uint32_t, timer.raw));
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}
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Timer::Timer(APIC *apic) : Interrupts::Handler(0) /* IRQ0 */
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{
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SmartCriticalSection(APICLock);
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this->lapic = apic;
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LVTTimerDivide Divider = DivideBy16;
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trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
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this->lapic->Write(APIC_TDCR, Divider);
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this->lapic->Write(APIC_TICR, 0xFFFFFFFF);
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TimeManager->Sleep(1, Time::Units::Milliseconds);
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// Mask the timer
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this->lapic->Write(APIC_TIMER, 0x10000 /* LVTTimer.Mask flag */);
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Ticks = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
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// Config for IRQ0 timer
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LVTTimer timer = {.raw = 0};
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timer.Vector = IRQ0;
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timer.Mask = Unmasked;
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timer.TimerMode = LVTTimerMode::OneShot;
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// Initialize APIC timer
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this->lapic->Write(APIC_TDCR, Divider);
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this->lapic->Write(APIC_TICR, s_cst(uint32_t, Ticks));
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this->lapic->Write(APIC_TIMER, s_cst(uint32_t, timer.raw));
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trace("%d APIC Timer %d ticks in.", GetCurrentCPU()->ID, Ticks);
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KPrint("APIC Timer: \e8888FF%ld\eCCCCCC ticks.", Ticks);
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}
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Timer::~Timer()
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{
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}
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}
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@@ -228,7 +228,14 @@ namespace GlobalDescriptorTable
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gdt[Core].Entries->TaskStateSegment.BaseLow = Base & 0xFFFF;
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gdt[Core].Entries->TaskStateSegment.BaseMiddle = uint8_t((Base >> 16) & 0xFF);
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gdt[Core].Entries->TaskStateSegment.BaseHigh = uint8_t((Base >> 24) & 0xFF);
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#pragma diagnostic push
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#pragma GCC diagnostic ignored "-Wshift-count-overflow"
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||||
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gdt[Core].Entries->TaskStateSegment.BaseUpper = s_cst(uint32_t, (Base >> 32) & 0xFFFFFFFF);
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#pragma diagnostic pop
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gdt[Core].Entries->TaskStateSegment.Access = {.A = 1, .RW = 0, .DC = 0, .E = 1, .S = 0, .DPL = 0, .P = 1};
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gdt[Core].Entries->TaskStateSegment.Granularity = (0 << 4) | ((Limit >> 16) & 0xF);
|
||||
|
||||
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File diff suppressed because it is too large
Load Diff
@@ -23,17 +23,27 @@
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||||
#include <cpu.hpp>
|
||||
#include <atomic>
|
||||
|
||||
#include <smp.hpp>
|
||||
|
||||
#include <memory.hpp>
|
||||
#include <ints.hpp>
|
||||
#include <assert.h>
|
||||
#include <cpu.hpp>
|
||||
#include <atomic>
|
||||
|
||||
#include "../../../kernel.h"
|
||||
#include "../acpi.hpp"
|
||||
#include "apic.hpp"
|
||||
|
||||
enum SMPTrampolineAddress
|
||||
{
|
||||
PAGE_TABLE = 0x500,
|
||||
START_ADDR = 0x520,
|
||||
STACK = 0x570,
|
||||
GDT = 0x580,
|
||||
IDT = 0x590,
|
||||
CORE = 0x600,
|
||||
TRAMPOLINE_START = 0x2000
|
||||
PAGE_TABLE = 0x500,
|
||||
START_ADDR = 0x520,
|
||||
STACK = 0x570,
|
||||
GDT = 0x580,
|
||||
IDT = 0x590,
|
||||
CORE = 0x600,
|
||||
TRAMPOLINE_START = 0x2000
|
||||
};
|
||||
|
||||
std::atomic_bool CPUEnabled = false;
|
||||
@@ -45,22 +55,33 @@ SafeFunction CPUData *GetCPU(long id) { return &CPUs[id]; }
|
||||
|
||||
SafeFunction CPUData *GetCurrentCPU()
|
||||
{
|
||||
uint64_t ret = 0;
|
||||
if (!(&CPUs[ret])->IsActive)
|
||||
{
|
||||
// error("CPU %d is not active!", ret); FIXME
|
||||
return &CPUs[0];
|
||||
}
|
||||
assert((&CPUs[ret])->Checksum == CPU_DATA_CHECKSUM);
|
||||
return &CPUs[ret];
|
||||
uint64_t ret = 0;
|
||||
if (!(&CPUs[ret])->IsActive)
|
||||
{
|
||||
// error("CPU %d is not active!", ret); FIXME
|
||||
return &CPUs[0];
|
||||
}
|
||||
assert((&CPUs[ret])->Checksum == CPU_DATA_CHECKSUM);
|
||||
return &CPUs[ret];
|
||||
}
|
||||
|
||||
namespace SMP
|
||||
{
|
||||
int CPUCores = 0;
|
||||
int CPUCores = 0;
|
||||
|
||||
void Initialize(void *madt)
|
||||
{
|
||||
fixme("SMP::Initialize() is not implemented!");
|
||||
}
|
||||
void Initialize(void *_madt)
|
||||
{
|
||||
ACPI::MADT *madt = (ACPI::MADT *)_madt;
|
||||
|
||||
int Cores = madt->CPUCores + 1;
|
||||
|
||||
if (Config.Cores > madt->CPUCores + 1)
|
||||
KPrint("More cores requested than available. Using %d cores", madt->CPUCores + 1);
|
||||
else if (Config.Cores != 0)
|
||||
Cores = Config.Cores;
|
||||
|
||||
CPUCores = Cores;
|
||||
|
||||
fixme("SMP::Initialize() is not implemented!");
|
||||
}
|
||||
}
|
||||
|
||||
@@ -25,330 +25,330 @@
|
||||
|
||||
namespace APIC
|
||||
{
|
||||
enum APICRegisters
|
||||
{
|
||||
// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
|
||||
APIC_ID = 0x20, // Local APIC ID
|
||||
APIC_VER = 0x30, // Local APIC Version
|
||||
APIC_TPR = 0x80, // Task Priority
|
||||
APIC_APR = 0x90, // Arbitration Priority
|
||||
APIC_PPR = 0xA0, // Processor Priority
|
||||
APIC_EOI = 0xB0, // EOI
|
||||
APIC_RRD = 0xC0, // Remote Read
|
||||
APIC_LDR = 0xD0, // Logical Destination
|
||||
APIC_DFR = 0xE0, // Destination Format
|
||||
APIC_SVR = 0xF0, // Spurious Interrupt Vector
|
||||
APIC_ISR = 0x100, // In-Service (8 registers)
|
||||
APIC_TMR = 0x180, // Trigger Mode (8 registers)
|
||||
APIC_IRR = 0x200, // Interrupt Request (8 registers)
|
||||
APIC_ESR = 0x280, // Error Status
|
||||
APIC_ICRLO = 0x300, // Interrupt Command
|
||||
APIC_ICRHI = 0x310, // Interrupt Command [63:32]
|
||||
APIC_TIMER = 0x320, // LVT Timer
|
||||
APIC_THERMAL = 0x330, // LVT Thermal Sensor
|
||||
APIC_PERF = 0x340, // LVT Performance Counter
|
||||
APIC_LINT0 = 0x350, // LVT LINT0
|
||||
APIC_LINT1 = 0x360, // LVT LINT1
|
||||
APIC_ERROR = 0x370, // LVT Error
|
||||
APIC_TICR = 0x380, // Initial Count (for Timer)
|
||||
APIC_TCCR = 0x390, // Current Count (for Timer)
|
||||
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
|
||||
};
|
||||
enum APICRegisters
|
||||
{
|
||||
// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
|
||||
APIC_ID = 0x20, // Local APIC ID
|
||||
APIC_VER = 0x30, // Local APIC Version
|
||||
APIC_TPR = 0x80, // Task Priority
|
||||
APIC_APR = 0x90, // Arbitration Priority
|
||||
APIC_PPR = 0xA0, // Processor Priority
|
||||
APIC_EOI = 0xB0, // EOI
|
||||
APIC_RRD = 0xC0, // Remote Read
|
||||
APIC_LDR = 0xD0, // Logical Destination
|
||||
APIC_DFR = 0xE0, // Destination Format
|
||||
APIC_SVR = 0xF0, // Spurious Interrupt Vector
|
||||
APIC_ISR = 0x100, // In-Service (8 registers)
|
||||
APIC_TMR = 0x180, // Trigger Mode (8 registers)
|
||||
APIC_IRR = 0x200, // Interrupt Request (8 registers)
|
||||
APIC_ESR = 0x280, // Error Status
|
||||
APIC_ICRLO = 0x300, // Interrupt Command
|
||||
APIC_ICRHI = 0x310, // Interrupt Command [63:32]
|
||||
APIC_TIMER = 0x320, // LVT Timer
|
||||
APIC_THERMAL = 0x330, // LVT Thermal Sensor
|
||||
APIC_PERF = 0x340, // LVT Performance Counter
|
||||
APIC_LINT0 = 0x350, // LVT LINT0
|
||||
APIC_LINT1 = 0x360, // LVT LINT1
|
||||
APIC_ERROR = 0x370, // LVT Error
|
||||
APIC_TICR = 0x380, // Initial Count (for Timer)
|
||||
APIC_TCCR = 0x390, // Current Count (for Timer)
|
||||
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
|
||||
};
|
||||
|
||||
enum IOAPICRegisters
|
||||
{
|
||||
GetIOAPICVersion = 0x1
|
||||
};
|
||||
enum IOAPICRegisters
|
||||
{
|
||||
GetIOAPICVersion = 0x1
|
||||
};
|
||||
|
||||
enum IOAPICFlags
|
||||
{
|
||||
ActiveHighLow = 2,
|
||||
EdgeLevel = 8
|
||||
};
|
||||
enum IOAPICFlags
|
||||
{
|
||||
ActiveHighLow = 2,
|
||||
EdgeLevel = 8
|
||||
};
|
||||
|
||||
enum APICDeliveryMode
|
||||
{
|
||||
Fixed = 0b000,
|
||||
LowestPriority = 0b001, /* Reserved */
|
||||
SMI = 0b010,
|
||||
APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
|
||||
NMI = 0b100,
|
||||
INIT = 0b101,
|
||||
Startup = 0b110,
|
||||
ExtINT = 0b111 /* Reserved */
|
||||
};
|
||||
enum APICDeliveryMode
|
||||
{
|
||||
Fixed = 0b000,
|
||||
LowestPriority = 0b001, /* Reserved */
|
||||
SMI = 0b010,
|
||||
APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
|
||||
NMI = 0b100,
|
||||
INIT = 0b101,
|
||||
Startup = 0b110,
|
||||
ExtINT = 0b111 /* Reserved */
|
||||
};
|
||||
|
||||
enum APICDestinationMode
|
||||
{
|
||||
Physical = 0b0,
|
||||
Logical = 0b1
|
||||
};
|
||||
enum APICDestinationMode
|
||||
{
|
||||
Physical = 0b0,
|
||||
Logical = 0b1
|
||||
};
|
||||
|
||||
enum APICDeliveryStatus
|
||||
{
|
||||
Idle = 0b0,
|
||||
SendPending = 0b1
|
||||
};
|
||||
enum APICDeliveryStatus
|
||||
{
|
||||
Idle = 0b0,
|
||||
SendPending = 0b1
|
||||
};
|
||||
|
||||
enum APICLevel
|
||||
{
|
||||
DeAssert = 0b0,
|
||||
Assert = 0b1
|
||||
};
|
||||
enum APICLevel
|
||||
{
|
||||
DeAssert = 0b0,
|
||||
Assert = 0b1
|
||||
};
|
||||
|
||||
enum APICTriggerMode
|
||||
{
|
||||
Edge = 0b0,
|
||||
Level = 0b1
|
||||
};
|
||||
enum APICTriggerMode
|
||||
{
|
||||
Edge = 0b0,
|
||||
Level = 0b1
|
||||
};
|
||||
|
||||
enum APICDestinationShorthand
|
||||
{
|
||||
NoShorthand = 0b00,
|
||||
Self = 0b01,
|
||||
AllIncludingSelf = 0b10,
|
||||
AllExcludingSelf = 0b11
|
||||
};
|
||||
enum APICDestinationShorthand
|
||||
{
|
||||
NoShorthand = 0b00,
|
||||
Self = 0b01,
|
||||
AllIncludingSelf = 0b10,
|
||||
AllExcludingSelf = 0b11
|
||||
};
|
||||
|
||||
enum LVTTimerDivide
|
||||
{
|
||||
DivideBy2 = 0b000,
|
||||
DivideBy4 = 0b001,
|
||||
DivideBy8 = 0b010,
|
||||
DivideBy16 = 0b011,
|
||||
DivideBy32 = 0b100,
|
||||
DivideBy64 = 0b101,
|
||||
DivideBy128 = 0b110,
|
||||
DivideBy1 = 0b111
|
||||
};
|
||||
enum LVTTimerDivide
|
||||
{
|
||||
DivideBy2 = 0b000,
|
||||
DivideBy4 = 0b001,
|
||||
DivideBy8 = 0b010,
|
||||
DivideBy16 = 0b011,
|
||||
DivideBy32 = 0b100,
|
||||
DivideBy64 = 0b101,
|
||||
DivideBy128 = 0b110,
|
||||
DivideBy1 = 0b111
|
||||
};
|
||||
|
||||
enum LVTTimerMask
|
||||
{
|
||||
Unmasked = 0b0,
|
||||
Masked = 0b1
|
||||
};
|
||||
enum LVTTimerMask
|
||||
{
|
||||
Unmasked = 0b0,
|
||||
Masked = 0b1
|
||||
};
|
||||
|
||||
enum LVTTimerMode
|
||||
{
|
||||
OneShot = 0b00,
|
||||
Periodic = 0b01,
|
||||
TSCDeadline = 0b10
|
||||
};
|
||||
enum LVTTimerMode
|
||||
{
|
||||
OneShot = 0b00,
|
||||
Periodic = 0b01,
|
||||
TSCDeadline = 0b10
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 4;
|
||||
/**
|
||||
* @brief Delivery Status
|
||||
*
|
||||
* 0: Idle
|
||||
* 1: Send Pending
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 3;
|
||||
/**
|
||||
* @brief Mask
|
||||
*
|
||||
* 0: Not masked
|
||||
* 1: Masked
|
||||
*/
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Timer Mode
|
||||
*
|
||||
* 0: One-shot
|
||||
* 1: Periodic
|
||||
* 2: TSC-Deadline
|
||||
*/
|
||||
uint64_t TimerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 14;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed LVTTimer;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 4;
|
||||
/**
|
||||
* @brief Delivery Status
|
||||
*
|
||||
* 0: Idle
|
||||
* 1: Send Pending
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 3;
|
||||
/**
|
||||
* @brief Mask
|
||||
*
|
||||
* 0: Not masked
|
||||
* 1: Masked
|
||||
*/
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Timer Mode
|
||||
*
|
||||
* 0: One-shot
|
||||
* 1: Periodic
|
||||
* 2: TSC-Deadline
|
||||
*/
|
||||
uint64_t TimerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 14;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed LVTTimer;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Spurious Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Enable or disable APIC software */
|
||||
uint64_t Software : 1;
|
||||
/** @brief Focus Processor Checking */
|
||||
uint64_t FocusProcessorChecking : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved : 2;
|
||||
/** @brief Disable EOI Broadcast */
|
||||
uint64_t DisableEOIBroadcast : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 19;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed Spurious;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Spurious Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Enable or disable APIC software */
|
||||
uint64_t Software : 1;
|
||||
/** @brief Focus Processor Checking */
|
||||
uint64_t FocusProcessorChecking : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved : 2;
|
||||
/** @brief Disable EOI Broadcast */
|
||||
uint64_t DisableEOIBroadcast : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 19;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed Spurious;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status
|
||||
*
|
||||
* @note Reserved when in x2APIC mode
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 1;
|
||||
/** @brief Level
|
||||
*
|
||||
* 0: Deassert
|
||||
* 1: Assert
|
||||
*/
|
||||
uint64_t Level : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 2;
|
||||
/** @brief Destination Shorthand
|
||||
*
|
||||
* 0: No shorthand
|
||||
* 1: Self
|
||||
* 2: All including self
|
||||
* 3: All excluding self
|
||||
*/
|
||||
uint64_t DestinationShorthand : 2;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 12;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed InterruptCommandRegisterLow;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status
|
||||
*
|
||||
* @note Reserved when in x2APIC mode
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 1;
|
||||
/** @brief Level
|
||||
*
|
||||
* 0: Deassert
|
||||
* 1: Assert
|
||||
*/
|
||||
uint64_t Level : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 2;
|
||||
/** @brief Destination Shorthand
|
||||
*
|
||||
* 0: No shorthand
|
||||
* 1: Self
|
||||
* 2: All including self
|
||||
* 3: All excluding self
|
||||
*/
|
||||
uint64_t DestinationShorthand : 2;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 12;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed InterruptCommandRegisterLow;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t Destination : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed InterruptCommandRegisterHigh;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t Destination : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed InterruptCommandRegisterHigh;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status */
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Interrupt Input Pin Polarity
|
||||
*
|
||||
* 0: Active High
|
||||
* 1: Active Low
|
||||
*/
|
||||
uint64_t Polarity : 1;
|
||||
/** @brief Remote IRR */
|
||||
uint64_t RemoteIRR : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Mask */
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 15;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t DestinationID : 8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint64_t Low;
|
||||
uint64_t High;
|
||||
} split;
|
||||
uint64_t raw;
|
||||
} __packed IOAPICRedirectEntry;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status */
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Interrupt Input Pin Polarity
|
||||
*
|
||||
* 0: Active High
|
||||
* 1: Active Low
|
||||
*/
|
||||
uint64_t Polarity : 1;
|
||||
/** @brief Remote IRR */
|
||||
uint64_t RemoteIRR : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Mask */
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 15;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t DestinationID : 8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint64_t Low;
|
||||
uint64_t High;
|
||||
} split;
|
||||
uint64_t raw;
|
||||
} __packed IOAPICRedirectEntry;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint64_t Version : 8;
|
||||
uint64_t Reserved : 8;
|
||||
uint64_t MaximumRedirectionEntry : 8;
|
||||
uint64_t Reserved2 : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed IOAPICVersion;
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint64_t Version : 8;
|
||||
uint64_t Reserved : 8;
|
||||
uint64_t MaximumRedirectionEntry : 8;
|
||||
uint64_t Reserved2 : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __packed IOAPICVersion;
|
||||
|
||||
class APIC
|
||||
{
|
||||
private:
|
||||
bool x2APICSupported = false;
|
||||
uint64_t APICBaseAddress = 0;
|
||||
class APIC
|
||||
{
|
||||
private:
|
||||
bool x2APICSupported = false;
|
||||
uint64_t APICBaseAddress = 0;
|
||||
|
||||
public:
|
||||
uint32_t Read(uint32_t Register);
|
||||
void Write(uint32_t Register, uint32_t Value);
|
||||
void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
|
||||
uint32_t IORead(uint64_t Base, uint32_t Register);
|
||||
void EOI();
|
||||
void RedirectIRQs(int CPU = 0);
|
||||
void WaitForIPI();
|
||||
void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
|
||||
void SendInitIPI(uint8_t CPU);
|
||||
void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
|
||||
uint32_t IOGetMaxRedirect(uint32_t APICID);
|
||||
void RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
|
||||
void RedirectIRQ(int CPU, uint16_t IRQ, int Status);
|
||||
APIC(int Core);
|
||||
~APIC();
|
||||
};
|
||||
public:
|
||||
uint32_t Read(uint32_t Register);
|
||||
void Write(uint32_t Register, uint32_t Value);
|
||||
void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
|
||||
uint32_t IORead(uint64_t Base, uint32_t Register);
|
||||
void EOI();
|
||||
void RedirectIRQs(int CPU = 0);
|
||||
void WaitForIPI();
|
||||
void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
|
||||
void SendInitIPI(uint8_t CPU);
|
||||
void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
|
||||
uint32_t IOGetMaxRedirect(uint32_t APICID);
|
||||
void RawRedirectIRQ(uint16_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
|
||||
void RedirectIRQ(int CPU, uint16_t IRQ, int Status);
|
||||
APIC(int Core);
|
||||
~APIC();
|
||||
};
|
||||
|
||||
class Timer : public Interrupts::Handler
|
||||
{
|
||||
private:
|
||||
APIC *lapic;
|
||||
uint64_t Ticks = 0;
|
||||
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
|
||||
class Timer : public Interrupts::Handler
|
||||
{
|
||||
private:
|
||||
APIC *lapic;
|
||||
uint64_t Ticks = 0;
|
||||
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
|
||||
|
||||
public:
|
||||
uint64_t GetTicks() { return Ticks; }
|
||||
void OneShot(uint32_t Vector, uint64_t Miliseconds);
|
||||
Timer(APIC *apic);
|
||||
~Timer();
|
||||
};
|
||||
public:
|
||||
uint64_t GetTicks() { return Ticks; }
|
||||
void OneShot(uint32_t Vector, uint64_t Miliseconds);
|
||||
Timer(APIC *apic);
|
||||
~Timer();
|
||||
};
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_APIC_H__
|
||||
|
||||
@@ -22,49 +22,49 @@
|
||||
|
||||
namespace InterruptDescriptorTable
|
||||
{
|
||||
typedef enum _InterruptGateType
|
||||
{
|
||||
TASK = 0b101,
|
||||
INT_16BIT = 0b110,
|
||||
TRAP_16BIT = 0b111,
|
||||
INT_32BIT = 0b1110,
|
||||
TRAP_32BIT = 0b1111,
|
||||
} InterruptGateType;
|
||||
typedef enum _InterruptGateType
|
||||
{
|
||||
TASK = 0b101,
|
||||
INT_16BIT = 0b110,
|
||||
TRAP_16BIT = 0b111,
|
||||
INT_32BIT = 0b1110,
|
||||
TRAP_32BIT = 0b1111,
|
||||
} InterruptGateType;
|
||||
|
||||
typedef enum _InterruptRingType
|
||||
{
|
||||
RING0 = 0b0,
|
||||
RING1 = 0b1,
|
||||
RING2 = 0b10,
|
||||
RING3 = 0b11,
|
||||
} InterruptRingType;
|
||||
typedef enum _InterruptRingType
|
||||
{
|
||||
RING0 = 0b0,
|
||||
RING1 = 0b1,
|
||||
RING2 = 0b10,
|
||||
RING3 = 0b11,
|
||||
} InterruptRingType;
|
||||
|
||||
typedef struct _InterruptDescriptorTableEntry
|
||||
{
|
||||
uint32_t LowOffset : 16;
|
||||
uint32_t SegmentSelector : 16;
|
||||
uint32_t Reserved0 : 5;
|
||||
uint32_t Flags : 4;
|
||||
uint32_t Reserved1 : 1;
|
||||
uint32_t Ring : 2;
|
||||
uint32_t Present : 1;
|
||||
uint32_t HighOffset : 16;
|
||||
} __packed InterruptDescriptorTableEntry;
|
||||
typedef struct _InterruptDescriptorTableEntry
|
||||
{
|
||||
uint32_t LowOffset : 16;
|
||||
uint32_t SegmentSelector : 16;
|
||||
uint32_t Reserved0 : 5;
|
||||
uint32_t Flags : 4;
|
||||
uint32_t Reserved1 : 1;
|
||||
uint32_t Ring : 2;
|
||||
uint32_t Present : 1;
|
||||
uint32_t HighOffset : 16;
|
||||
} __packed InterruptDescriptorTableEntry;
|
||||
|
||||
typedef struct _InterruptDescriptorTableDescriptor
|
||||
{
|
||||
uint16_t Length;
|
||||
InterruptDescriptorTableEntry *Entries;
|
||||
} __packed InterruptDescriptorTableDescriptor;
|
||||
typedef struct _InterruptDescriptorTableDescriptor
|
||||
{
|
||||
uint16_t Length;
|
||||
InterruptDescriptorTableEntry *Entries;
|
||||
} __packed InterruptDescriptorTableDescriptor;
|
||||
|
||||
void SetEntry(uint8_t Index,
|
||||
void (*Base)(),
|
||||
InterruptGateType Gate,
|
||||
InterruptRingType Ring,
|
||||
bool Present,
|
||||
uint16_t SegmentSelector);
|
||||
void SetEntry(uint8_t Index,
|
||||
void (*Base)(),
|
||||
InterruptGateType Gate,
|
||||
InterruptRingType Ring,
|
||||
bool Present,
|
||||
uint16_t SegmentSelector);
|
||||
|
||||
void Init(int Core);
|
||||
void Init(int Core);
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_IDT_H__
|
||||
|
||||
Reference in New Issue
Block a user