Fennix/Kernel
1
0
Fork 0
mirror of https://github.com/Fennix-Project/Kernel.git synced 2025-07-11 15:29:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Rename "SafeFunction" macro to "NoSecurityAnalysis"

Browse Source
This commit is contained in:
EnderIce2
2024-02-04 04:31:30 +02:00
parent 11221b205a
commit b0575ba4f2
31 changed files with 157 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
include/cpu/x86/x64/cr.hpp
View File

@ -190,7 +190,7 @@ namespace CPU
} XCR0;
#if defined(a64)
SafeFunction static inline CR0 readcr0()
nsa static inline CR0 readcr0()
{
uint64_t Result = 0;
asmv("mov %%cr0, %[Result]"
@ -198,7 +198,7 @@ namespace CPU
return (CR0){.raw = Result};
}
SafeFunction static inline CR2 readcr2()
nsa static inline CR2 readcr2()
{
uint64_t Result = 0;
asmv("mov %%cr2, %[Result]"
@ -206,7 +206,7 @@ namespace CPU
return (CR2){.raw = Result};
}
SafeFunction static inline CR3 readcr3()
nsa static inline CR3 readcr3()
{
uint64_t Result = 0;
asmv("mov %%cr3, %[Result]"
@ -214,7 +214,7 @@ namespace CPU
return (CR3){.raw = Result};
}
SafeFunction static inline CR4 readcr4()
nsa static inline CR4 readcr4()
{
uint64_t Result = 0;
asmv("mov %%cr4, %[Result]"
@ -222,7 +222,7 @@ namespace CPU
return (CR4){.raw = Result};
}
SafeFunction static inline CR8 readcr8()
nsa static inline CR8 readcr8()
{
uint64_t Result = 0;
asmv("mov %%cr8, %[Result]"
@ -230,7 +230,7 @@ namespace CPU
return (CR8){.raw = Result};
}
SafeFunction static inline XCR0 readxcr0()
nsa static inline XCR0 readxcr0()
{
uint64_t Result = 0;
asmv("xgetbv"
@ -240,7 +240,7 @@ namespace CPU
return (XCR0){.raw = Result};
}
SafeFunction static inline void writecr0(CR0 ControlRegister)
nsa static inline void writecr0(CR0 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr0"
:
@ -248,7 +248,7 @@ namespace CPU
: "memory");
}
SafeFunction static inline void writecr2(CR2 ControlRegister)
nsa static inline void writecr2(CR2 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr2"
:
@ -256,7 +256,7 @@ namespace CPU
: "memory");
}
SafeFunction static inline void writecr3(CR3 ControlRegister)
nsa static inline void writecr3(CR3 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr3"
:
@ -264,7 +264,7 @@ namespace CPU
: "memory");
}
SafeFunction static inline void writecr4(CR4 ControlRegister)
nsa static inline void writecr4(CR4 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr4"
:
@ -272,7 +272,7 @@ namespace CPU
: "memory");
}
SafeFunction static inline void writecr8(CR8 ControlRegister)
nsa static inline void writecr8(CR8 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr8"
:
@ -280,7 +280,7 @@ namespace CPU
: "memory");
}
SafeFunction static inline void writexcr0(XCR0 ControlRegister)
nsa static inline void writexcr0(XCR0 ControlRegister)
{
asmv("xsetbv"
:

4
include/cpu/x86/x64/msr.hpp
View File

@ -402,7 +402,7 @@ namespace CPU
};
#if defined(a64)
SafeFunction static inline uint64_t rdmsr(uint32_t msr)
nsa static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;
asmv("rdmsr"
@ -412,7 +412,7 @@ namespace CPU
return ((uint64_t)Low) | (((uint64_t)High) << 32);
}
SafeFunction static inline void wrmsr(uint32_t msr, uint64_t Value)
nsa static inline void wrmsr(uint32_t msr, uint64_t Value)
{
uint32_t Low = s_cst(uint32_t, Value), High = s_cst(uint32_t, Value >> 32);
asmv("wrmsr"