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https://github.com/Fennix-Project/Kernel.git
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Fixed PCI BAR mapping
This commit is contained in:
Alex
parent
102da7b7ec
commit
9a1a7b9955
GPG Key ID:
EACC3AD603BAB4DD
@ -14,6 +14,119 @@
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namespace Driver
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{
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void Driver::MapPCIAddresses(PCI::PCIDeviceHeader *PCIDevice)
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{
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Memory::Virtual vma = Memory::Virtual(nullptr);
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debug("Header Type: %d", PCIDevice->HeaderType);
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switch (PCIDevice->HeaderType)
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{
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case 0: // PCI Header 0
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{
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uint32_t BAR[6] = {0};
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size_t BARsSize[6] = {0};
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BAR[0] = ((PCI::PCIHeader0 *)PCIDevice)->BAR0;
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BAR[1] = ((PCI::PCIHeader0 *)PCIDevice)->BAR1;
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BAR[2] = ((PCI::PCIHeader0 *)PCIDevice)->BAR2;
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BAR[3] = ((PCI::PCIHeader0 *)PCIDevice)->BAR3;
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BAR[4] = ((PCI::PCIHeader0 *)PCIDevice)->BAR4;
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BAR[5] = ((PCI::PCIHeader0 *)PCIDevice)->BAR5;
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uintptr_t BAR_Type = BAR[0] & 1;
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uintptr_t BAR_IOBase = BAR[1] & (~3);
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uintptr_t BAR_MemoryBase = BAR[0] & (~15);
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debug("Type: %d; IOBase: %#lx; MemoryBase: %#lx", BAR_Type, BAR_IOBase, BAR_MemoryBase);
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for (size_t i = 0; i < 6; i++)
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{
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if (BAR[i] == 0)
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continue;
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debug("BAR%d: %#lx", i, BAR[i]);
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}
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/* BARs Size */
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for (size_t i = 0; i < 6; i++)
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{
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if (BAR[i] == 0)
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continue;
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if ((BAR[i] & 1) == 0) // Memory Base
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{
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 = 0xFFFFFFFF;
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size_t size = ((PCI::PCIHeader0 *)PCIDevice)->BAR0;
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 = BAR[i];
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BARsSize[i] = size & (~15);
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BARsSize[i] = ~BARsSize[i] + 1;
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BARsSize[i] = BARsSize[i] & 0xFFFFFFFF;
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debug("BAR%dSize: %#lx", i, BARsSize[i]);
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}
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else if ((BAR[i] & 1) == 1) // I/O Base
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{
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((PCI::PCIHeader0 *)PCIDevice)->BAR1 = 0xFFFFFFFF;
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size_t size = ((PCI::PCIHeader0 *)PCIDevice)->BAR1;
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((PCI::PCIHeader0 *)PCIDevice)->BAR1 = BAR[i];
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BARsSize[i] = size & (~3);
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BARsSize[i] = ~BARsSize[i] + 1;
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BARsSize[i] = BARsSize[i] & 0xFFFF;
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debug("BAR%dSize: %#lx", i, BARsSize[i]);
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}
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}
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/* Mapping the BARs */
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for (size_t i = 0; i < 6; i++)
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{
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if (BAR[i] == 0)
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continue;
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if ((BAR[i] & 1) == 0) // Memory Base
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{
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uintptr_t BARBase = BAR[i] & (~15);
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size_t BARSize = BARsSize[i];
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debug("Mapping BAR%d from %#lx to %#lx", i, BARBase, BARBase + BARSize);
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for (uintptr_t j = BARBase;
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j < (BARBase + BARSize);
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j += PAGE_SIZE)
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{
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vma.Map((void *)j, (void *)j, Memory::PTFlag::RW | Memory::PTFlag::PWT);
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}
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}
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else if ((BAR[i] & 1) == 1) // I/O Base
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{
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uintptr_t BARBase = BAR[i] & (~3);
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uintptr_t BARSize = BARsSize[i];
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debug("Mapping BAR%d from %#x to %#x", i, BARBase, BARBase + BARSize);
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for (uintptr_t j = BARBase;
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j < (BARBase + BARSize);
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j += PAGE_SIZE)
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{
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vma.Map((void *)j, (void *)j, Memory::PTFlag::RW | Memory::PTFlag::PWT);
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}
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}
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}
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break;
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}
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case 1: // PCI Header 1 (PCI-to-PCI Bridge)
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{
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fixme("PCI Header 1 (PCI-to-PCI Bridge) not implemented yet");
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break;
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}
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case 2: // PCI Header 2 (PCI-to-CardBus Bridge)
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{
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fixme("PCI Header 2 (PCI-to-CardBus Bridge) not implemented yet");
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break;
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}
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default:
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{
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error("Unknown header type %d", PCIDevice->HeaderType);
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return;
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}
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}
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}
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DriverCode Driver::BindPCIGeneric(Memory::MemMgr *mem, void *fex, PCI::PCIDeviceHeader *PCIDevice)
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{
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FexExtended *fexExtended = (FexExtended *)((uintptr_t)fex + EXTENDED_SECTION_ADDRESS);
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@ -317,31 +430,7 @@ namespace Driver
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}
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debug("Starting driver %s", fexExtended->Driver.Name);
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debug("Type: %d; IOBase: %#x; MemoryBase: %#x",
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 & 1,
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((PCI::PCIHeader0 *)PCIDevice)->BAR1 & (~3),
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 & (~15));
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if ((((PCI::PCIHeader0 *)PCIDevice)->BAR0 & 1) != 0)
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if (!Memory::Virtual().Check((void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR1 & (~3))))
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{
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debug("IO base (BAR1 & ~3) is not mapped");
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Memory::Virtual().Map((void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR1 & (~3)), (void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR1 & (~3)), Memory::PTFlag::RW);
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}
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if ((((PCI::PCIHeader0 *)PCIDevice)->BAR0 & 1) == 0)
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if (!Memory::Virtual().Check((void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR0 & (~15))))
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{
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debug("Memory base (BAR0 & ~15) is not mapped");
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Memory::Virtual().Map((void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR0 & (~15)), (void *)(uintptr_t)(((PCI::PCIHeader0 *)PCIDevice)->BAR0 & (~15)), Memory::PTFlag::RW);
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uintptr_t original = ((PCI::PCIHeader0 *)PCIDevice)->BAR0;
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 = 0xFFFFFFFF;
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uintptr_t size = ((PCI::PCIHeader0 *)PCIDevice)->BAR0 & 0xFFFFFFF0;
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((PCI::PCIHeader0 *)PCIDevice)->BAR0 = original;
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debug("Size: %#lx (%ld pages)", size, TO_PAGES(size));
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fixme("TODO: [BUG] Mapping is broken!!!!!!");
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}
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MapPCIAddresses(PCIDevice);
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switch (fexExtended->Driver.Type)
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{
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@ -91,6 +91,10 @@
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* https://en.wikipedia.org/wiki/Inter-process_communication
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* https://www.geeksforgeeks.org/inter-process-communication-ipc/
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*
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* - PCI:
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* https://wiki.osdev.org/PCI
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* https://en.wikipedia.org/wiki/PCI_configuration_space
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*
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*/
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#ifdef a64
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@ -62,6 +62,7 @@ namespace Driver
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unsigned long DriverUIDs = 0;
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DriverCode CallDriverEntryPoint(void *fex, void *KAPIAddress);
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void MapPCIAddresses(PCI::PCIDeviceHeader *PCIDevice);
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DriverCode BindPCIGeneric(Memory::MemMgr *mem, void *fex, PCI::PCIDeviceHeader *PCIDevice);
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DriverCode BindPCIDisplay(Memory::MemMgr *mem, void *fex, PCI::PCIDeviceHeader *PCIDevice);
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DriverCode BindPCINetwork(Memory::MemMgr *mem, void *fex, PCI::PCIDeviceHeader *PCIDevice);
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@ -104,6 +104,10 @@ namespace PCI
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uint8_t BIST;
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};
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/**
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* @brief PCI Header Type 0
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*
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*/
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struct PCIHeader0
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{
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PCIDeviceHeader Header;
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@ -113,20 +117,82 @@ namespace PCI
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uint32_t BAR3;
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uint32_t BAR4;
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uint32_t BAR5;
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uint32_t CardbusCISPtr;
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uint32_t CardbusCISPointer;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t ExpansionROMBaseAddr;
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uint8_t CapabilitiesPtr;
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uint8_t Rsv0;
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uint16_t Rsv1;
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uint32_t Rsv2;
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uint32_t ExpansionROMBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t Reserved2;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint8_t MinGrant;
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uint8_t MaxLatency;
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};
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/**
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* @brief PCI Header Type 1 (PCI-to-PCI Bridge)
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*/
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struct PCIHeader1
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint8_t PrimaryBusNumber;
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uint8_t SecondaryBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t SecondaryLatencyTimer;
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uint8_t IOBase;
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uint8_t IOLimit;
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uint16_t SecondaryStatus;
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uint16_t MemoryBase;
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uint16_t MemoryLimit;
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uint16_t PrefetchableMemoryBase;
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uint16_t PrefetchableMemoryLimit;
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uint32_t PrefetchableMemoryBaseUpper32;
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uint32_t PrefetchableMemoryLimitUpper32;
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uint16_t IOBaseUpper16;
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uint16_t IOLimitUpper16;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t ExpansionROMBaseAddress;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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};
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/**
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* @brief PCI Header Type 2 (PCI-to-CardBus Bridge)
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*/
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struct PCIHeader2
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{
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PCIDeviceHeader Header;
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uint32_t CardbusSocketRegistersBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t SecondaryStatus;
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uint8_t PCIbusNumber;
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uint8_t CardbusBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t CardbusLatencyTimer;
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uint32_t MemoryBase0;
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uint32_t MemoryLimit0;
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uint32_t MemoryBase1;
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uint32_t MemoryLimit1;
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uint32_t IOBase0;
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uint32_t IOLimit0;
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uint32_t IOBase1;
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uint32_t IOLimit1;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t LegacyBaseAddress;
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};
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struct DeviceConfig
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{
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uintptr_t BaseAddress;
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