mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-07-11 07:19:20 +00:00
Update kernel
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@ -33,7 +33,7 @@ using namespace CPU::x64;
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using namespace CPU::x86;
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/*
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In constructor ‘APIC::APIC::APIC(int)’:
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In constructor 'APIC::APIC::APIC(int)':
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warning: left shift count >= width of type
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| APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
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| ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
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@ -55,8 +55,8 @@ namespace APIC
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debug("APIC::Read(%#lx) [x2=%d]",
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Register, x2APICSupported ? 1 : 0);
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#endif
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if (x2APICSupported)
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assert(false);
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if (unlikely(x2APICSupported))
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assert(!"x2APIC is not supported");
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
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@ -76,8 +76,8 @@ namespace APIC
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debug("APIC::Write(%#lx, %#lx) [x2=%d]",
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Register, Value, x2APICSupported ? 1 : 0);
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#endif
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if (x2APICSupported)
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assert(false);
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if (unlikely(x2APICSupported))
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assert(!"x2APIC is not supported");
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
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@ -107,6 +107,8 @@ namespace APIC
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void APIC::EOI()
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{
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Memory::SwapPT swap =
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Memory::SwapPT(KernelPageTable, thisPageTable);
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if (this->x2APICSupported)
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wrmsr(MSR_X2APIC_EOI, 0);
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else
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@ -396,20 +398,18 @@ namespace APIC
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APIC::~APIC() {}
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void Timer::OnInterruptReceived(TrapFrame *Frame) { UNUSED(Frame); }
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void Timer::OnInterruptReceived(CPU::TrapFrame *Frame) { UNUSED(Frame); }
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void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
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{
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SmartCriticalSection(APICLock);
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/* FIXME: Sometimes APIC stops firing when debugging, why? */
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LVTTimer timer{};
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timer.VEC = uint8_t(Vector);
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timer.TMM = LVTTimerMode::OneShot;
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LVTTimerDivide Divider = DivideBy8;
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if (unlikely(strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0))
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Divider = DivideBy128;
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SmartCriticalSection(APICLock);
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if (this->lapic->x2APIC)
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{
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// wrmsr(MSR_X2APIC_DIV_CONF, Divider); <- gpf on real hardware
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@ -373,7 +373,7 @@ namespace APIC
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private:
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APIC *lapic;
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uint64_t Ticks = 0;
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void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
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void OnInterruptReceived(CPU::TrapFrame *Frame);
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public:
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uint64_t GetTicks() { return Ticks; }
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@ -122,7 +122,7 @@ namespace GlobalDescriptorTable
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SafeFunction void Init(int Core)
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{
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memcpy(&GDTEntries[Core], &GDTEntriesTemplate, sizeof(GlobalDescriptorTableEntries));
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GDTEntries[Core] = GDTEntriesTemplate;
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gdt[Core] =
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{
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.Limit = sizeof(GlobalDescriptorTableEntries) - 1,
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@ -25,7 +25,7 @@
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#include "gdt.hpp"
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#include "../../../kernel.h"
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/* conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘unsigned char:2’ may change value */
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/* conversion from 'uint64_t' {aka 'long unsigned int'} to 'unsigned char:2' may change value */
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#pragma GCC diagnostic ignored "-Wconversion"
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extern "C" void MainInterruptHandler(void *Data);
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@ -532,11 +532,11 @@ namespace InterruptDescriptorTable
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}
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bool EnableISRs = true;
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#ifdef DEBUG
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// #ifdef DEBUG
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EnableISRs = !DebuggerIsAttached;
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if (!EnableISRs)
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KPrint("\eFFA500The debugger is attached, disabling all ISRs.");
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#endif
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// #endif
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/* ISR */
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SetEntry(0x0, InterruptHandler_0x0, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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@ -553,7 +553,7 @@ namespace InterruptDescriptorTable
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SetEntry(0xb, InterruptHandler_0xb, IST1, TRAP_GATE_64BIT, RING0, (!DebuggerIsAttached), GDT_KERNEL_CODE);
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SetEntry(0xc, InterruptHandler_0xc, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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SetEntry(0xd, InterruptHandler_0xd, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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SetEntry(0xe, InterruptHandler_0xe, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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SetEntry(0xe, InterruptHandler_0xe, IST3, TRAP_GATE_64BIT, RING0, EnableISRs /* FIXME: CoW? */, GDT_KERNEL_CODE);
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SetEntry(0xf, InterruptHandler_0xf, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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SetEntry(0x10, InterruptHandler_0x10, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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SetEntry(0x11, InterruptHandler_0x11, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
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@ -57,6 +57,9 @@ SafeFunction CPUData *GetCurrentCPU()
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int CoreID = 0;
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if (CPUEnabled.load(std::memory_order_acquire) == true)
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{
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Memory::SwapPT swap =
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Memory::SwapPT(KernelPageTable, thisPageTable);
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if (apic->x2APIC)
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CoreID = int(CPU::x64::rdmsr(CPU::x64::MSR_X2APIC_APICID));
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else
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@ -125,7 +128,8 @@ namespace SMP
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(uintptr_t)&_trampoline_start;
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Memory::Virtual().Map(0x0, 0x0, Memory::PTFlag::RW);
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/* We reserved the TRAMPOLINE_START address inside Physical class. */
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Memory::Virtual().Map((void *)TRAMPOLINE_START, (void *)TRAMPOLINE_START,
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Memory::Virtual().Map((void *)TRAMPOLINE_START,
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(void *)TRAMPOLINE_START,
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TrampolineLength, Memory::PTFlag::RW);
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memcpy((void *)TRAMPOLINE_START, &_trampoline_start, TrampolineLength);
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debug("Trampoline address: %#lx-%#lx",
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