Fennix/Kernel
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Update kernel

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This commit is contained in:
EnderIce2
2024-01-19 06:47:42 +02:00
parent fd15592608
commit 96daa43d38
282 changed files with 25486 additions and 15700 deletions
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20
arch/amd64/cpu/apic.cpp
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@ -33,7 +33,7 @@ using namespace CPU::x64;
using namespace CPU::x86;
/*
In constructor ‘APIC::APIC::APIC(int)’:
In constructor 'APIC::APIC::APIC(int)':
warning: left shift count >= width of type
| APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
| ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
@ -55,8 +55,8 @@ namespace APIC
debug("APIC::Read(%#lx) [x2=%d]",
Register, x2APICSupported ? 1 : 0);
#endif
if (x2APICSupported)
assert(false);
if (unlikely(x2APICSupported))
assert(!"x2APIC is not supported");
CPU::MemBar::Barrier();
uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
@ -76,8 +76,8 @@ namespace APIC
debug("APIC::Write(%#lx, %#lx) [x2=%d]",
Register, Value, x2APICSupported ? 1 : 0);
#endif
if (x2APICSupported)
assert(false);
if (unlikely(x2APICSupported))
assert(!"x2APIC is not supported");
CPU::MemBar::Barrier();
*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
@ -107,6 +107,8 @@ namespace APIC
void APIC::EOI()
{
Memory::SwapPT swap =
Memory::SwapPT(KernelPageTable, thisPageTable);
if (this->x2APICSupported)
wrmsr(MSR_X2APIC_EOI, 0);
else
@ -396,20 +398,18 @@ namespace APIC
APIC::~APIC() {}
void Timer::OnInterruptReceived(TrapFrame *Frame) { UNUSED(Frame); }
void Timer::OnInterruptReceived(CPU::TrapFrame *Frame) { UNUSED(Frame); }
void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
{
SmartCriticalSection(APICLock);
/* FIXME: Sometimes APIC stops firing when debugging, why? */
LVTTimer timer{};
timer.VEC = uint8_t(Vector);
timer.TMM = LVTTimerMode::OneShot;
LVTTimerDivide Divider = DivideBy8;
if (unlikely(strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0))
Divider = DivideBy128;
SmartCriticalSection(APICLock);
if (this->lapic->x2APIC)
{
// wrmsr(MSR_X2APIC_DIV_CONF, Divider); <- gpf on real hardware

2
arch/amd64/cpu/apic.hpp
View File

@ -373,7 +373,7 @@ namespace APIC
private:
APIC *lapic;
uint64_t Ticks = 0;
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
void OnInterruptReceived(CPU::TrapFrame *Frame);
public:
uint64_t GetTicks() { return Ticks; }

2
arch/amd64/cpu/gdt.cpp
View File

@ -122,7 +122,7 @@ namespace GlobalDescriptorTable
SafeFunction void Init(int Core)
{
memcpy(&GDTEntries[Core], &GDTEntriesTemplate, sizeof(GlobalDescriptorTableEntries));
GDTEntries[Core] = GDTEntriesTemplate;
gdt[Core] =
{
.Limit = sizeof(GlobalDescriptorTableEntries) - 1,

8
arch/amd64/cpu/idt.cpp
View File

@ -25,7 +25,7 @@
#include "gdt.hpp"
#include "../../../kernel.h"
/* conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘unsigned char:2’ may change value */
/* conversion from 'uint64_t' {aka 'long unsigned int'} to 'unsigned char:2' may change value */
#pragma GCC diagnostic ignored "-Wconversion"
extern "C" void MainInterruptHandler(void *Data);
@ -532,11 +532,11 @@ namespace InterruptDescriptorTable
}
bool EnableISRs = true;
#ifdef DEBUG
// #ifdef DEBUG
EnableISRs = !DebuggerIsAttached;
if (!EnableISRs)
KPrint("\eFFA500The debugger is attached, disabling all ISRs.");
#endif
// #endif
/* ISR */
SetEntry(0x0, InterruptHandler_0x0, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
@ -553,7 +553,7 @@ namespace InterruptDescriptorTable
SetEntry(0xb, InterruptHandler_0xb, IST1, TRAP_GATE_64BIT, RING0, (!DebuggerIsAttached), GDT_KERNEL_CODE);
SetEntry(0xc, InterruptHandler_0xc, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0xd, InterruptHandler_0xd, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0xe, InterruptHandler_0xe, IST3, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0xe, InterruptHandler_0xe, IST3, TRAP_GATE_64BIT, RING0, EnableISRs /* FIXME: CoW? */, GDT_KERNEL_CODE);
SetEntry(0xf, InterruptHandler_0xf, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x10, InterruptHandler_0x10, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x11, InterruptHandler_0x11, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);

6
arch/amd64/cpu/smp.cpp
View File

@ -57,6 +57,9 @@ SafeFunction CPUData *GetCurrentCPU()
int CoreID = 0;
if (CPUEnabled.load(std::memory_order_acquire) == true)
{
Memory::SwapPT swap =
Memory::SwapPT(KernelPageTable, thisPageTable);
if (apic->x2APIC)
CoreID = int(CPU::x64::rdmsr(CPU::x64::MSR_X2APIC_APICID));
else
@ -125,7 +128,8 @@ namespace SMP
(uintptr_t)&_trampoline_start;
Memory::Virtual().Map(0x0, 0x0, Memory::PTFlag::RW);
/* We reserved the TRAMPOLINE_START address inside Physical class. */
Memory::Virtual().Map((void *)TRAMPOLINE_START, (void *)TRAMPOLINE_START,
Memory::Virtual().Map((void *)TRAMPOLINE_START,
(void *)TRAMPOLINE_START,
TrampolineLength, Memory::PTFlag::RW);
memcpy((void *)TRAMPOLINE_START, &_trampoline_start, TrampolineLength);
debug("Trampoline address: %#lx-%#lx",