mirror of
https://github.com/Fennix-Project/Kernel.git
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Restructured and rewritten entire codebase
This commit is contained in:
Alex
388
modules/AudioCodec97/AudioCodec97.cpp
Normal file
388
modules/AudioCodec97/AudioCodec97.cpp
Normal file
@ -0,0 +1,388 @@
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/*
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This file is part of Fennix Kernel.
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||||
|
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Fennix Kernel is free software: you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation, either version 3 of
|
||||
the License, or (at your option) any later version.
|
||||
|
||||
Fennix Kernel is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "ac97.hpp"
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#include <debug.h>
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#include <pci.hpp>
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#include <io.h>
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#include "../../mapi.hpp"
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#include "../mod.hpp"
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using namespace PCI;
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namespace AudioCodec97
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{
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KernelAPI KAPI;
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/* https://wiki.osdev.org/AC97 */
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PCIDeviceHeader *PCIBaseAddress;
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BARData BAR;
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BufferDescriptorList *DescriptorList = nullptr;
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AudioEncodingValues Encoding = AE_PCMs16le;
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char Channels = 2;
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uint8_t Volume = AV_Maximum;
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bool Mute = false;
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int SampleRate = 48000;
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char SampleSize = 2;
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uint16_t MixerVolume(uint8_t Left, uint8_t Right, bool Mute)
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{
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return ((uint16_t)((Right & 0x3F) |
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((Left & 0x3F) << 0x8) |
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(Mute & 1 << 0xF)));
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}
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int DriverEntry(void *Data)
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{
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if (!Data)
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return INVALID_KERNEL_API;
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KAPI = *(KernelAPI *)Data;
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if (KAPI.Version.Major < 0 || KAPI.Version.Minor < 0 || KAPI.Version.Patch < 0)
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return KERNEL_API_VERSION_NOT_SUPPORTED;
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return OK;
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}
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int CallbackHandler(KernelCallback *Data)
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{
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switch (Data->Reason)
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{
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case AcknowledgeReason:
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{
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debug("Kernel acknowledged the driver.");
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break;
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}
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case ConfigurationReason:
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{
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debug("Module received configuration data.");
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PCIBaseAddress = reinterpret_cast<PCIDeviceHeader *>(Data->RawPtr);
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PCIBaseAddress->Command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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/* Native Audio Mixer Base Address */
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uint32_t PCIBAR0 = ((PCIHeader0 *)PCIBaseAddress)->BAR0;
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/* Native Audio Bus Master Base Address */
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uint32_t PCIBAR1 = ((PCIHeader0 *)PCIBaseAddress)->BAR1;
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BAR.Type = PCIBAR0 & 1;
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BAR.MixerAddress = (uint16_t)(PCIBAR0 & (~3));
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BAR.BusMasterAddress = PCIBAR1 & (~15);
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if (BAR.Type != 1)
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{
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error("BAR0 is not I/O.");
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return INVALID_PCI_BAR;
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}
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uint16_t OutputPCMTransferControl = (uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl);
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/* DescriptorList address MUST be physical. */
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DescriptorList = (BufferDescriptorList *)KAPI.Memory.RequestPage((sizeof(BufferDescriptorList) * DescriptorListLength) / KAPI.Memory.PageSize + 1);
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memset(DescriptorList, 0, sizeof(BufferDescriptorList) * DescriptorListLength);
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uint16_t DLSampleCount = (uint16_t)(KAPI.Memory.PageSize / SampleSize);
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for (int i = 0; i < DescriptorListLength; i++)
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{
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int DescriptorPages = (int)(sizeof(uint16_t *) / KAPI.Memory.PageSize + 1);
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DescriptorList[i].Address = (uint32_t)(uint64_t)KAPI.Memory.RequestPage(DescriptorPages);
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DescriptorList[i].SampleCount = DLSampleCount;
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DescriptorList[i].Flags = 0;
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debug("DescriptorList[%d] = { Address: 0x%x (%d %s), SampleCount: %d, Flags: 0x%x }",
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i,
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DescriptorList[i].Address, DescriptorPages, DescriptorPages == 1 ? "page" : "pages",
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DescriptorList[i].SampleCount,
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DescriptorList[i].Flags);
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}
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outw(BAR.MixerAddress + NAM_MasterVolume, MixerVolume(Volume, Volume, Mute));
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outw(BAR.MixerAddress + NAM_PCMOutVolume, MixerVolume(Volume, Volume, Mute));
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outb(OutputPCMTransferControl, inb(OutputPCMTransferControl) | TC_TransferReset);
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while (inb(OutputPCMTransferControl) & TC_TransferReset)
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;
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uint32_t GlobalControl = inl((uint16_t)(BAR.BusMasterAddress + NABM_GlobalControl));
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GlobalControl = (GlobalControl & ~((0x3U) << 22)); /* PCM 16-bit mode */
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GlobalControl = (GlobalControl & ~((0x3U) << 20)); /* 2 channels */
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GlobalControl |= GC_GlobalInterruptEnable;
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GlobalControl &= ~GC_ShutDown;
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outl((uint16_t)(BAR.BusMasterAddress + PCMOUT_BufferDescriptorList), (uint32_t)(uint64_t)DescriptorList);
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outl((uint16_t)(BAR.BusMasterAddress + NABM_GlobalControl), GlobalControl);
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uint8_t TransferControl = inb(OutputPCMTransferControl);
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TransferControl |= TC_LastBufferEntryInterruptEnable | TC_IOCInterruptEnable | TC_FifoERRORInterruptEnable;
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outb(OutputPCMTransferControl, TransferControl);
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// Stop DMA
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outb(OutputPCMTransferControl, inb(OutputPCMTransferControl) & ~TC_DMAControllerControl);
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debug("AC'97 configured.");
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break;
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}
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case AdjustReason:
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{
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if (Data->AudioCallback.Adjust._Volume)
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{
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Volume = (uint8_t)(0x3F - (0x3F * Data->AudioCallback.Adjust.Volume / 100));
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outw(BAR.MixerAddress + NAM_MasterVolume, MixerVolume(Volume, Volume, Mute));
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// outw(BAR.MixerAddress + NAM_PCMOutVolume, MixerVolume(Volume, Volume, Mute));
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}
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else if (Data->AudioCallback.Adjust._Encoding)
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{
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fixme("Encoding changing not supported yet.");
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}
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else if (Data->AudioCallback.Adjust._SampleRate)
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{
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switch (Data->AudioCallback.Adjust.SampleRate)
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{
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case 0:
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{
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SampleRate = 8000;
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break;
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}
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case 1:
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{
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SampleRate = 11025;
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break;
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}
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case 2:
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{
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SampleRate = 16000;
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break;
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}
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case 3:
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{
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SampleRate = 22050;
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break;
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}
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case 4:
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{
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SampleRate = 32000;
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break;
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}
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case 5:
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{
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SampleRate = 44100;
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break;
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}
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case 6:
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{
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SampleRate = 48000;
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break;
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}
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case 7:
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{
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SampleRate = 88200;
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break;
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}
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case 8:
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{
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SampleRate = 96000;
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break;
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}
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default:
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{
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SampleRate = 16000;
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error("Invalid sample rate. Defaulting to 16000.");
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break;
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}
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}
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}
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else if (Data->AudioCallback.Adjust._Channels)
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{
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switch (Data->AudioCallback.Adjust.Channels)
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{
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case 0:
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{
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Channels = 1; // Mono
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break;
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}
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case 1:
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{
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Channels = 2; // Stereo
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break;
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}
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default:
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{
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Channels = 2;
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error("Invalid channel count. Defaulting to 2.");
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break;
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}
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}
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}
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break;
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}
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case QueryReason:
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{
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Data->AudioCallback.Fetch.Volume = (unsigned char)((inw(BAR.MixerAddress + NAM_MasterVolume) & 0x3F) * 100 / 0x3F);
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Data->AudioCallback.Fetch.Encoding = Encoding; /* FIXME */
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// Data->AudioCallback.Fetch.SampleRate = SampleRate; /* FIXME */
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Data->AudioCallback.Fetch.Channels = Channels;
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break;
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}
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case SendReason:
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{
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unsigned char *Buffer = (unsigned char *)Data->AudioCallback.Send.Data;
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unsigned int Length = (unsigned int)Data->AudioCallback.Send.Length;
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if (Buffer == nullptr)
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{
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error("Invalid buffer.");
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return INVALID_DATA;
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}
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if ((Length == 0) || (Length % (SampleSize * Channels)))
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{
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error("Invalid buffer length.");
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return INVALID_DATA;
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}
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int TotalBDLToFill = (int)((Length + KAPI.Memory.PageSize - 1) >> 12);
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while (Length > 0)
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{
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bool ActiveDMA = !(inw((uint16_t)(BAR.BusMasterAddress + PCMOUT_Status)) & TC_DMAControllerControl);
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if (ActiveDMA)
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{
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int RemainingBDL = 0;
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do
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{
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int CurrentBDL = inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_BufferDescriptorEntry));
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int LastBDL = inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_DescriptorEntries));
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RemainingBDL = LastBDL - CurrentBDL;
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if (RemainingBDL < 0)
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RemainingBDL += DescriptorListLength;
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RemainingBDL += 1;
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if (RemainingBDL >= DescriptorListLength - 1)
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{
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long SampleCount = DescriptorList[(CurrentBDL + 1) % DescriptorListLength].SampleCount / Channels;
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if (SampleCount > 0)
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KAPI.Util.Sleep(SampleCount * 1000 / SampleRate); // milliseconds
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}
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} while (RemainingBDL >= DescriptorListLength - 1 && !(inw((uint16_t)(BAR.BusMasterAddress + PCMOUT_Status)) & TC_DMAControllerControl));
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}
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{
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uint8_t CurrentBDL = inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_BufferDescriptorEntry));
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uint8_t LastBDL = inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_DescriptorEntries));
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uint8_t NextBDL = LastBDL % DescriptorListLength;
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ActiveDMA = !(inw((uint16_t)(BAR.BusMasterAddress + PCMOUT_Status)) & TC_DMAControllerControl);
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if (ActiveDMA)
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{
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NextBDL = (uint8_t)((LastBDL + 1) % DescriptorListLength);
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if (NextBDL == CurrentBDL)
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continue;
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}
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do
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{
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size_t Wrote = (KAPI.Memory.PageSize > Length) ? size_t(Length)
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: size_t(KAPI.Memory.PageSize);
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if (Wrote == 0)
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break;
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memcpy((void *)((uint64_t)DescriptorList[NextBDL].Address), Buffer, Wrote);
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DescriptorList[NextBDL].Flags = 0;
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Buffer += Wrote;
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Length -= (unsigned int)Wrote;
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DescriptorList[NextBDL].SampleCount = (uint16_t)(Wrote / SampleSize);
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TotalBDLToFill--;
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NextBDL = (uint8_t)((NextBDL + 1) % DescriptorListLength);
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} while (TotalBDLToFill-- && NextBDL != CurrentBDL);
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outb((uint16_t)(BAR.BusMasterAddress + PCMOUT_DescriptorEntries), NextBDL - 1);
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ActiveDMA = !(inw((uint16_t)(BAR.BusMasterAddress + PCMOUT_Status)) & TC_DMAControllerControl);
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if (!ActiveDMA)
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{
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// Start DMA
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outb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl), inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl) | TC_DMAControllerControl));
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}
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}
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}
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break;
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}
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case StopReason:
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{
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outw(BAR.MixerAddress + NAM_MasterVolume, MixerVolume(AV_Maximum, AV_Maximum, true));
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outw(BAR.MixerAddress + NAM_PCMOutVolume, MixerVolume(AV_Maximum, AV_Maximum, true));
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// Stop DMA
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outb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl), inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl)) & ~TC_DMAControllerControl);
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// Disable interrupts
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uint8_t TransferControl = inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl));
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TransferControl &= ~(TC_LastBufferEntryInterruptEnable | TC_IOCInterruptEnable | TC_FifoERRORInterruptEnable);
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outb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl), TransferControl);
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|
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// Disable global control
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uint32_t GlobalControl = inl((uint16_t)(BAR.BusMasterAddress + NABM_GlobalControl));
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GlobalControl &= ~GC_GlobalInterruptEnable;
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GlobalControl |= GC_ShutDown;
|
||||
outl((uint16_t)(BAR.BusMasterAddress + NABM_GlobalControl), GlobalControl);
|
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|
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debug("Module stopped.");
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
warn("Unknown reason.");
|
||||
break;
|
||||
}
|
||||
}
|
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return OK;
|
||||
}
|
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|
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int InterruptCallback(CPURegisters *)
|
||||
{
|
||||
uint16_t Status = inw(BAR.MixerAddress + PCMOUT_Status);
|
||||
|
||||
if (Status & TC_IOCInterruptEnable)
|
||||
{
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debug("Interrupt on completion.");
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||||
}
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else if (Status & TC_LastBufferEntryInterruptEnable)
|
||||
{
|
||||
debug("Last buffer entry.");
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// Stop DMA
|
||||
outb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl), inb((uint16_t)(BAR.BusMasterAddress + PCMOUT_TransferControl)) & ~TC_DMAControllerControl);
|
||||
}
|
||||
else if (Status & TC_FifoERRORInterruptEnable)
|
||||
{
|
||||
debug("FIFO error.");
|
||||
}
|
||||
else if (Status != 0x0)
|
||||
{
|
||||
error("Unknown status: %#lx", Status);
|
||||
}
|
||||
|
||||
outw(BAR.MixerAddress + PCMOUT_Status, 0xFFFF);
|
||||
return OK;
|
||||
}
|
||||
}
|
||||
348
modules/AudioCodec97/ac97.hpp
Normal file
348
modules/AudioCodec97/ac97.hpp
Normal file
@ -0,0 +1,348 @@
|
||||
/*
|
||||
This file is part of Fennix Kernel.
|
||||
|
||||
Fennix Kernel is free software: you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation, either version 3 of
|
||||
the License, or (at your option) any later version.
|
||||
|
||||
Fennix Kernel is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __FENNIX_KERNEL_AC97_H__
|
||||
#define __FENNIX_KERNEL_AC97_H__
|
||||
|
||||
#include <types.h>
|
||||
#include "../../mapi.hpp"
|
||||
|
||||
namespace AudioCodec97
|
||||
{
|
||||
#define DescriptorListLength 0x20
|
||||
|
||||
enum AudioVolumeValues
|
||||
{
|
||||
AV_Maximum = 0x0,
|
||||
AV_Minimum = 0x3F,
|
||||
};
|
||||
|
||||
enum AudioEncodingValues
|
||||
{
|
||||
AE_PCMs8,
|
||||
AE_PCMu8,
|
||||
|
||||
AE_PCMs16le,
|
||||
AE_PCMs20le,
|
||||
AE_PCMs24le,
|
||||
AE_PCMs32le,
|
||||
|
||||
AE_PCMu16le,
|
||||
AE_PCMu20le,
|
||||
AE_PCMu24le,
|
||||
AE_PCMu32le,
|
||||
|
||||
AE_PCMs16be,
|
||||
AE_PCMs20be,
|
||||
AE_PCMs24be,
|
||||
AE_PCMs32be,
|
||||
|
||||
AE_PCMu16be,
|
||||
AE_PCMu20be,
|
||||
AE_PCMu24be,
|
||||
AE_PCMu32be,
|
||||
};
|
||||
|
||||
enum NativeAudioMixerRegisters
|
||||
{
|
||||
/**
|
||||
* @brief Reset Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_Reset = 0x00,
|
||||
|
||||
/**
|
||||
* @brief Master Volume Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_MasterVolume = 0x02,
|
||||
|
||||
/**
|
||||
* @brief Microphone Volume Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_MicrophoneVolume = 0x0E,
|
||||
|
||||
/**
|
||||
* @brief PCM Out Volume Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_PCMOutVolume = 0x18,
|
||||
|
||||
/**
|
||||
* @brief Select Record Input Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_SelectRecordInput = 0x1A,
|
||||
|
||||
/**
|
||||
* @brief Record Gain Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_RecordGain = 0x1C,
|
||||
|
||||
/**
|
||||
* @brief Record Gain Microphone Register
|
||||
* @note Length: word
|
||||
*/
|
||||
NAM_RecordGainMicrophone = 0x1E,
|
||||
};
|
||||
|
||||
enum NativeAudioBusMasterRegisters
|
||||
{
|
||||
/**
|
||||
* @brief Register box for PCM IN
|
||||
* @note Length: below
|
||||
*/
|
||||
NABM_PCMInBox = 0x00,
|
||||
|
||||
/**
|
||||
* @brief Register box for PCM OUT
|
||||
* @note Length: below
|
||||
*/
|
||||
NABM_PCMOutBox = 0x10,
|
||||
|
||||
/**
|
||||
* @brief Register box for Microphone
|
||||
* @note Length: below
|
||||
*/
|
||||
NABM_MicrophoneBox = 0x20,
|
||||
|
||||
/**
|
||||
* @brief Global Control Register
|
||||
* @note Length: dword
|
||||
*/
|
||||
NABM_GlobalControl = 0x2C, /* 0x30 */
|
||||
|
||||
/**
|
||||
* @brief Global Status Register
|
||||
* @note Length: dword
|
||||
*/
|
||||
NABM_GlobalStatus = 0x30, /* 0x34 */
|
||||
};
|
||||
|
||||
enum NativeAudioBusMasterBoxOffsets
|
||||
{
|
||||
/**
|
||||
* @brief Physical Address of Buffer Descriptor List
|
||||
* @note Length: dword
|
||||
*/
|
||||
NABMBOFF_BufferDescriptorList = 0x00,
|
||||
|
||||
/**
|
||||
* @brief Number of Actual Processed Buffer Descriptor Entry
|
||||
* @note Length: byte
|
||||
*/
|
||||
NABMBOFF_BufferDescriptorEntry = 0x04,
|
||||
|
||||
/**
|
||||
* @brief Number of all Descriptor Entries
|
||||
* @note Length: byte
|
||||
*/
|
||||
NABMBOFF_DescriptorEntries = 0x05,
|
||||
|
||||
/**
|
||||
* @brief Status of transferring Data
|
||||
* @note Length: word
|
||||
*/
|
||||
NABMBOFF_Status = 0x06,
|
||||
|
||||
/**
|
||||
* @brief Number of transferred Samples in Actual Processed Entry
|
||||
* @note Length: word
|
||||
*/
|
||||
NABMBOFF_TransferredSamples = 0x08,
|
||||
|
||||
/**
|
||||
* @brief Number of next processed Buffer Entry
|
||||
* @note Length: byte
|
||||
*/
|
||||
NABMBOFF_NextProcessedBufferEntry = 0x0A,
|
||||
|
||||
/**
|
||||
* @brief Transfer Control
|
||||
* @note Length: byte
|
||||
*/
|
||||
NABMBOFF_TransferControl = 0x0B,
|
||||
};
|
||||
|
||||
enum OutputPulseCodeModulationRegisters
|
||||
{
|
||||
/**
|
||||
* @brief Physical Address of Buffer Descriptor List
|
||||
* @note Length: dword
|
||||
*/
|
||||
PCMOUT_BufferDescriptorList = (int)NABM_PCMOutBox + (int)NABMBOFF_BufferDescriptorList,
|
||||
|
||||
/**
|
||||
* @brief Number of Actual Processed Buffer Descriptor Entry
|
||||
* @note Length: byte
|
||||
*/
|
||||
PCMOUT_BufferDescriptorEntry = (int)NABM_PCMOutBox + (int)NABMBOFF_BufferDescriptorEntry,
|
||||
|
||||
/**
|
||||
* @brief Number of all Descriptor Entries
|
||||
* @note Length: byte
|
||||
*/
|
||||
PCMOUT_DescriptorEntries = (int)NABM_PCMOutBox + (int)NABMBOFF_DescriptorEntries,
|
||||
|
||||
/**
|
||||
* @brief Status of transferring Data
|
||||
* @note Length: word
|
||||
*/
|
||||
PCMOUT_Status = (int)NABM_PCMOutBox + (int)NABMBOFF_Status,
|
||||
|
||||
/**
|
||||
* @brief Number of transferred Samples in Actual Processed Entry
|
||||
* @note Length: word
|
||||
*/
|
||||
PCMOUT_TransferredSamples = (int)NABM_PCMOutBox + (int)NABMBOFF_TransferredSamples,
|
||||
|
||||
/**
|
||||
* @brief Number of next processed Buffer Entry
|
||||
* @note Length: byte
|
||||
*/
|
||||
PCMOUT_NextProcessedBufferEntry = (int)NABM_PCMOutBox + (int)NABMBOFF_NextProcessedBufferEntry,
|
||||
|
||||
/**
|
||||
* @brief Transfer Control
|
||||
* @note Length: byte
|
||||
*/
|
||||
PCMOUT_TransferControl = (int)NABM_PCMOutBox + (int)NABMBOFF_TransferControl,
|
||||
};
|
||||
|
||||
enum TransferControlRegisters
|
||||
{
|
||||
/**
|
||||
* @brief DMA controller control
|
||||
* 0 = Pause transfer
|
||||
* 1 = Transfer sound data
|
||||
*/
|
||||
TC_DMAControllerControl = 0x01,
|
||||
|
||||
/**
|
||||
* @brief Reset
|
||||
* 0 = Remove reset condition
|
||||
* 1 = Reset this NABM register box, this bit is cleared by card when is reset complete
|
||||
*/
|
||||
TC_TransferReset = 0x02,
|
||||
|
||||
/**
|
||||
* @brief Last Buffer Entry Interrupt enable
|
||||
* 0 = Disable interrupt
|
||||
* 1 = Enable interrupt
|
||||
*/
|
||||
TC_LastBufferEntryInterruptEnable = 0x04,
|
||||
|
||||
/**
|
||||
* @brief IOC Interrupt enable
|
||||
* 0 = Disable interrupt
|
||||
* 1 = Enable interrupt
|
||||
*/
|
||||
TC_IOCInterruptEnable = 0x08,
|
||||
|
||||
/**
|
||||
* @brief Fifo ERROR Interrupt enable
|
||||
* 0 = Disable interrupt
|
||||
* 1 = Enable interrupt
|
||||
*/
|
||||
TC_FifoERRORInterruptEnable = 0x10,
|
||||
};
|
||||
|
||||
enum GlobalControlRegisters
|
||||
{
|
||||
/**
|
||||
* @brief Global Interrupt Enable
|
||||
* 0 = Disable Interrupts
|
||||
* 1 = Enable Interrupts
|
||||
*/
|
||||
GC_GlobalInterruptEnable = 0x01,
|
||||
|
||||
/**
|
||||
* @brief Cold reset
|
||||
* 0 = Device is in reset and can not be used
|
||||
* 1 = Resume to operational state
|
||||
*/
|
||||
GC_ColdReset = 0x02,
|
||||
|
||||
/**
|
||||
* @brief Warm reset
|
||||
*/
|
||||
GC_WarmReset = 0x04,
|
||||
|
||||
/**
|
||||
* @brief Shut down
|
||||
* 0 = Device is powered
|
||||
* 1 = Shut down
|
||||
*/
|
||||
GC_ShutDown = 0x08,
|
||||
|
||||
/**
|
||||
* @brief Channels for PCM Output
|
||||
* 00 = 2 channels
|
||||
* 01 = 4 channels
|
||||
* 10 = 6 channels
|
||||
* 11 = Reserved
|
||||
*/
|
||||
GC_ChannelsForPCMOutput = 0x30,
|
||||
|
||||
/**
|
||||
* @brief PCM Output mode
|
||||
* 00 = 16 bit samples
|
||||
* 01 = 20 bit samples
|
||||
*/
|
||||
GC_PCMOutputMode = 0xC0,
|
||||
};
|
||||
|
||||
struct BufferDescriptorList
|
||||
{
|
||||
/**
|
||||
* @brief Physical Address to sound data in memory
|
||||
* @note Length: dword
|
||||
*/
|
||||
uint32_t Address;
|
||||
|
||||
/**
|
||||
* @brief Number of samples in this buffer
|
||||
* @note Length: word
|
||||
*/
|
||||
uint16_t SampleCount;
|
||||
|
||||
/**
|
||||
* @brief Flags
|
||||
* @note Length: word
|
||||
*
|
||||
* Bit 15 = Interrupt fired when data from this entry is transferred
|
||||
* Bit 14 = Last entry of buffer, stop playing
|
||||
* Other bits = Reserved
|
||||
*/
|
||||
uint16_t Flags;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct BARData
|
||||
{
|
||||
uint8_t Type;
|
||||
uint16_t MixerAddress;
|
||||
uint64_t BusMasterAddress;
|
||||
};
|
||||
|
||||
int DriverEntry(void *);
|
||||
int CallbackHandler(KernelCallback *);
|
||||
int InterruptCallback(CPURegisters *);
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_AC97_H__
|
||||
Reference in New Issue
Block a user