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Restructured and rewritten entire codebase
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Alex
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modules/AHCI/ahci.hpp
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193
modules/AHCI/ahci.hpp
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_AHCI_H__
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#define __FENNIX_KERNEL_AHCI_H__
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#include <types.h>
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#include "../../mapi.hpp"
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namespace AdvancedHostControllerInterface
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{
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#define ATA_DEV_BUSY 0x80
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#define ATA_DEV_DRQ 0x08
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#define ATA_CMD_WRITE_DMA_EX 0x35
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#define ATA_CMD_READ_DMA_EX 0x25
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#define HBA_PxIS_TFES (1 << 30)
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#define HBA_PORT_DEV_PRESENT 0x3
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#define HBA_PORT_IPM_ACTIVE 0x1
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#define SATA_SIG_ATAPI 0xEB140101
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#define SATA_SIG_ATA 0x00000101
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#define SATA_SIG_SEMB 0xC33C0101
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#define SATA_SIG_PM 0x96690101
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#define HBA_PxCMD_CR 0x8000
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#define HBA_PxCMD_FRE 0x0010
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#define HBA_PxCMD_ST 0x0001
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#define HBA_PxCMD_FR 0x4000
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enum PortType
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{
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None = 0,
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SATA = 1,
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SEMB = 2,
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PM = 3,
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SATAPI = 4,
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};
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enum FIS_TYPE
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{
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FIS_TYPE_REG_H2D = 0x27,
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FIS_TYPE_REG_D2H = 0x34,
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FIS_TYPE_DMA_ACT = 0x39,
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FIS_TYPE_DMA_SETUP = 0x41,
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FIS_TYPE_DATA = 0x46,
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FIS_TYPE_BIST = 0x58,
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FIS_TYPE_PIO_SETUP = 0x5F,
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FIS_TYPE_DEV_BITS = 0xA1,
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};
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struct HBAPort
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{
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uint32_t CommandListBase;
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uint32_t CommandListBaseUpper;
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uint32_t FISBaseAddress;
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uint32_t FISBaseAddressUpper;
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uint32_t InterruptStatus;
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uint32_t InterruptEnable;
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uint32_t CommandStatus;
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uint32_t Reserved0;
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uint32_t TaskFileData;
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uint32_t Signature;
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uint32_t SataStatus;
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uint32_t SataControl;
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uint32_t SataError;
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uint32_t SataActive;
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uint32_t CommandIssue;
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uint32_t SataNotification;
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uint32_t FISSwitchControl;
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uint32_t Reserved1[11];
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uint32_t Vendor[4];
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};
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struct HBAMemory
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{
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uint32_t HostCapability;
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uint32_t GlobalHostControl;
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uint32_t InterruptStatus;
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uint32_t PortsImplemented;
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uint32_t Version;
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uint32_t CCCControl;
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uint32_t CCCPorts;
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uint32_t EnclosureManagementLocation;
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uint32_t EnclosureManagementControl;
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uint32_t HostCapabilitiesExtended;
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uint32_t BIOSHandoffControlStatus;
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uint8_t Reserved0[0x74];
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uint8_t Vendor[0x60];
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HBAPort Ports[1];
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};
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struct HBACommandHeader
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{
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uint8_t CommandFISLength : 5;
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uint8_t ATAPI : 1;
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uint8_t Write : 1;
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uint8_t Preferable : 1;
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uint8_t Reset : 1;
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uint8_t BIST : 1;
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uint8_t ClearBusy : 1;
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uint8_t Reserved0 : 1;
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uint8_t PortMultiplier : 4;
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uint16_t PRDTLength;
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uint32_t PRDBCount;
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uint32_t CommandTableBaseAddress;
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uint32_t CommandTableBaseAddressUpper;
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uint32_t Reserved1[4];
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};
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struct HBAPRDTEntry
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{
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uint32_t DataBaseAddress;
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uint32_t DataBaseAddressUpper;
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uint32_t Reserved0;
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uint32_t ByteCount : 22;
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uint32_t Reserved1 : 9;
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uint32_t InterruptOnCompletion : 1;
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};
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struct HBACommandTable
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{
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uint8_t CommandFIS[64];
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uint8_t ATAPICommand[16];
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uint8_t Reserved[48];
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HBAPRDTEntry PRDTEntry[];
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};
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struct FIS_REG_H2D
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{
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uint8_t FISType;
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uint8_t PortMultiplier : 4;
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uint8_t Reserved0 : 3;
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uint8_t CommandControl : 1;
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uint8_t Command;
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uint8_t FeatureLow;
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uint8_t LBA0;
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uint8_t LBA1;
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uint8_t LBA2;
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uint8_t DeviceRegister;
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uint8_t LBA3;
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uint8_t LBA4;
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uint8_t LBA5;
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uint8_t FeatureHigh;
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uint8_t CountLow;
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uint8_t CountHigh;
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uint8_t ISOCommandCompletion;
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uint8_t Control;
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uint8_t Reserved1[4];
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};
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struct BARData
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{
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uint8_t Type;
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uint16_t IOBase;
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uint64_t MemoryBase;
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};
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class Port
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{
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public:
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PortType AHCIPortType;
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HBAPort *HBAPortPtr;
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uint8_t *Buffer;
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uint8_t PortNumber;
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Port(PortType Type, HBAPort *PortPtr, uint8_t PortNumber);
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~Port();
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void StartCMD();
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void StopCMD();
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void Configure();
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bool ReadWrite(uint64_t Sector, uint32_t SectorCount, uint8_t *Buffer, bool Write);
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};
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int DriverEntry(void *);
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int CallbackHandler(KernelCallback *);
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int InterruptCallback(CPURegisters *);
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}
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#endif // !__FENNIX_KERNEL_AHCI_H__
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