Restructured and rewritten entire codebase

arch/i386/arithmetic_operations.c

@@ -0,0 +1,379 @@
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wfloat-equal"
+
+/* Source: https://github.com/glitchub/arith64 */
+#define arith64_u64 unsigned long long int
+#define arith64_s64 signed long long int
+#define arith64_u32 unsigned int
+#define arith64_s32 int
+
+typedef union
+{
+	arith64_u64 u64;
+	arith64_s64 s64;
+	struct
+	{
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		arith64_u32 hi;
+		arith64_u32 lo;
+#else
+		arith64_u32 lo;
+		arith64_u32 hi;
+#endif
+	} u32;
+	struct
+	{
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		arith64_s32 hi;
+		arith64_s32 lo;
+#else
+		arith64_s32 lo;
+		arith64_s32 hi;
+#endif
+	} s32;
+} arith64_word;
+
+#define arith64_hi(n) (arith64_word){.u64 = n}.u32.hi
+#define arith64_lo(n) (arith64_word){.u64 = n}.u32.lo
+#define arith64_neg(a, b) (((a) ^ ((((arith64_s64)(b)) >= 0) - 1)) + (((arith64_s64)(b)) < 0))
+#define arith64_abs(a) arith64_neg(a, a)
+
+arith64_s64 __absvdi2(arith64_s64 a)
+{
+	return arith64_abs(a);
+}
+
+arith64_s64 __ashldi3(arith64_s64 a, int b)
+{
+	arith64_word w = {.s64 = a};
+
+	b &= 63;
+
+	if (b >= 32)
+	{
+		w.u32.hi = w.u32.lo << (b - 32);
+		w.u32.lo = 0;
+	}
+	else if (b)
+	{
+		w.u32.hi = (w.u32.lo >> (32 - b)) | (w.u32.hi << b);
+		w.u32.lo <<= b;
+	}
+	return w.s64;
+}
+
+arith64_s64 __ashrdi3(arith64_s64 a, int b)
+{
+	arith64_word w = {.s64 = a};
+
+	b &= 63;
+
+	if (b >= 32)
+	{
+		w.s32.lo = w.s32.hi >> (b - 32);
+		w.s32.hi >>= 31; // 0xFFFFFFFF or 0
+	}
+	else if (b)
+	{
+		w.u32.lo = (w.u32.hi << (32 - b)) | (w.u32.lo >> b);
+		w.s32.hi >>= b;
+	}
+	return w.s64;
+}
+
+int __clzsi2(arith64_u32 a)
+{
+	int b, n = 0;
+	b = !(a & 0xffff0000) << 4;
+	n += b;
+	a <<= b;
+	b = !(a & 0xff000000) << 3;
+	n += b;
+	a <<= b;
+	b = !(a & 0xf0000000) << 2;
+	n += b;
+	a <<= b;
+	b = !(a & 0xc0000000) << 1;
+	n += b;
+	a <<= b;
+	return n + !(a & 0x80000000);
+}
+
+int __clzdi2(arith64_u64 a)
+{
+	int b, n = 0;
+	b = !(a & 0xffffffff00000000ULL) << 5;
+	n += b;
+	a <<= b;
+	b = !(a & 0xffff000000000000ULL) << 4;
+	n += b;
+	a <<= b;
+	b = !(a & 0xff00000000000000ULL) << 3;
+	n += b;
+	a <<= b;
+	b = !(a & 0xf000000000000000ULL) << 2;
+	n += b;
+	a <<= b;
+	b = !(a & 0xc000000000000000ULL) << 1;
+	n += b;
+	a <<= b;
+	return n + !(a & 0x8000000000000000ULL);
+}
+
+int __ctzsi2(arith64_u32 a)
+{
+	int b, n = 0;
+	b = !(a & 0x0000ffff) << 4;
+	n += b;
+	a >>= b;
+	b = !(a & 0x000000ff) << 3;
+	n += b;
+	a >>= b;
+	b = !(a & 0x0000000f) << 2;
+	n += b;
+	a >>= b;
+	b = !(a & 0x00000003) << 1;
+	n += b;
+	a >>= b;
+	return n + !(a & 0x00000001);
+}
+
+int __ctzdi2(arith64_u64 a)
+{
+	int b, n = 0;
+	b = !(a & 0x00000000ffffffffULL) << 5;
+	n += b;
+	a >>= b;
+	b = !(a & 0x000000000000ffffULL) << 4;
+	n += b;
+	a >>= b;
+	b = !(a & 0x00000000000000ffULL) << 3;
+	n += b;
+	a >>= b;
+	b = !(a & 0x000000000000000fULL) << 2;
+	n += b;
+	a >>= b;
+	b = !(a & 0x0000000000000003ULL) << 1;
+	n += b;
+	a >>= b;
+	return n + !(a & 0x0000000000000001ULL);
+}
+
+arith64_u64 __divmoddi4(arith64_u64 a, arith64_u64 b, arith64_u64 *c)
+{
+	if (b > a)
+	{
+		if (c)
+			*c = a;
+		return 0;
+	}
+	if (!arith64_hi(b))
+	{
+		if (b == 0)
+		{
+			volatile char x = 0;
+			x = 1 / x;
+		}
+		if (b == 1)
+		{
+			if (c)
+				*c = 0;
+			return a;
+		}
+		if (!arith64_hi(a))
+		{
+			if (c)
+				*c = arith64_lo(a) % arith64_lo(b);
+			return arith64_lo(a) / arith64_lo(b);
+		}
+	}
+
+	char bits = __clzdi2(b) - __clzdi2(a) + 1;
+	arith64_u64 rem = a >> bits;
+	a <<= 64 - bits;
+	arith64_u64 wrap = 0;
+	while (bits-- > 0)
+	{
+		rem = (rem << 1) | (a >> 63);
+		a = (a << 1) | (wrap & 1);
+		wrap = ((arith64_s64)(b - rem - 1) >> 63);
+		rem -= b & wrap;
+	}
+	if (c)
+		*c = rem;
+	return (a << 1) | (wrap & 1);
+}
+
+arith64_s64 __divdi3(arith64_s64 a, arith64_s64 b)
+{
+	arith64_u64 q = __divmoddi4(arith64_abs(a), arith64_abs(b), (void *)0);
+	return arith64_neg(q, a ^ b);
+}
+
+int __ffsdi2(arith64_u64 a) { return a ? __ctzdi2(a) + 1 : 0; }
+
+arith64_u64 __lshrdi3(arith64_u64 a, int b)
+{
+	arith64_word w = {.u64 = a};
+
+	b &= 63;
+
+	if (b >= 32)
+	{
+		w.u32.lo = w.u32.hi >> (b - 32);
+		w.u32.hi = 0;
+	}
+	else if (b)
+	{
+		w.u32.lo = (w.u32.hi << (32 - b)) | (w.u32.lo >> b);
+		w.u32.hi >>= b;
+	}
+	return w.u64;
+}
+
+arith64_s64 __moddi3(arith64_s64 a, arith64_s64 b)
+{
+	arith64_u64 r;
+	__divmoddi4(arith64_abs(a), arith64_abs(b), &r);
+	return arith64_neg(r, a);
+}
+
+int __popcountsi2(arith64_u32 a)
+{
+
+	a = a - ((a >> 1) & 0x55555555);
+	a = ((a >> 2) & 0x33333333) + (a & 0x33333333);
+	a = (a + (a >> 4)) & 0x0F0F0F0F;
+	a = (a + (a >> 16));
+
+	return (a + (a >> 8)) & 63;
+}
+
+int __popcountdi2(arith64_u64 a)
+{
+
+	a = a - ((a >> 1) & 0x5555555555555555ULL);
+	a = ((a >> 2) & 0x3333333333333333ULL) + (a & 0x3333333333333333ULL);
+	a = (a + (a >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+	a = (a + (a >> 32));
+	a = (a + (a >> 16));
+
+	return (a + (a >> 8)) & 127;
+}
+
+arith64_u64 __udivdi3(arith64_u64 a, arith64_u64 b) { return __divmoddi4(a, b, (void *)0); }
+
+arith64_u64 __umoddi3(arith64_u64 a, arith64_u64 b)
+{
+	arith64_u64 r;
+	__divmoddi4(a, b, &r);
+	return r;
+}
+
+/* Good documentation: https://splichal.eu/scripts/sphinx/gccint/_build/html/the-gcc-low-level-runtime-library/routines-for-floating-point-emulation.html */
+
+double __adddf3(double a, double b) { return a + b; }
+double __muldf3(double a, double b) { return a * b; }
+double __floatsidf(int i) { return (double)i; }
+int __ltdf2(double a, double b) { return a < b; }
+int __gtdf2(double a, double b) { return a > b; }
+int __nedf2(double a, double b) { return a != b; }
+int __eqdf2(double a, double b) { return a == b; }
+double __floatdidf(long i) { return (double)i; }
+double __divdf3(double a, double b) { return a / b; }
+double __subdf3(double a, double b) { return a - b; }
+int __gedf2(double a, double b) { return a >= b; }
+int __fixdfsi(double a) { return (int)a; }
+long __fixdfdi(double a) { return (long)a; }
+int __ledf2(double a, double b) { return a <= b; }
+
+/* FIXME: Check if these functions are implemented correctly */
+
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+typedef unsigned int uint32_t;
+typedef struct
+{
+	uint64_t value;
+} atomic_uint64_t;
+
+/* No longer needed? */
+
+// uint64_t __atomic_load_8(const atomic_uint64_t *p)
+// {
+// 	uint64_t value;
+// 	__asm__ volatile("lock cmpxchg8b %1"
+// 					 : "=A"(value)
+// 					 : "m"(*p)
+// 					 : "memory");
+// 	return value;
+// }
+
+// void __atomic_store_8(atomic_uint64_t *p, uint64_t value)
+// {
+// 	__asm__ volatile("lock cmpxchg8b %0"
+// 					 : "=m"(p->value)
+// 					 : "a"((uint32_t)value), "d"((uint32_t)(value >> 32)), "m"(*p)
+// 					 : "memory");
+// }
+
+int __fixsfsi(float a)
+{
+	return (int)a;
+}
+
+int __ltsf2(float a, float b)
+{
+	return -(a < b);
+}
+
+int __nesf2(float a, float b)
+{
+	return a == b;
+}
+
+int __eqsf2(float a, float b)
+{
+	return !(a == b);
+}
+
+float __divsf3(float a, float b)
+{
+	return (a / b);
+}
+
+double __extendsfdf2(float a)
+{
+	return (double)a;
+}
+
+float __truncdfsf2(double a)
+{
+	return (float)a;
+}
+
+float __subsf3(float a, float b)
+{
+	return (a - b);
+}
+
+float __floatsisf(int a)
+{
+	return (float)a;
+}
+
+int __fixunssfsi(float a)
+{
+	return (int)a;
+}
+
+float __mulsf3(float a, float b)
+{
+	return (a * b);
+}
+
+float __addsf3(float a, float b)
+{
+	return (a + b);
+}

arch/i386/bootstrap/Multiboot/Paging/mb_pt.s

@@ -0,0 +1,51 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.code32
+KERNEL_VIRTUAL_BASE = 0xC0000000 /* 3GB */
+KERNEL_PAGE_NUMBER = 768 /* KERNEL_VIRTUAL_BASE >> 22 */
+
+.section .bootstrap.data, "a"
+.align 0x1000
+.global BootPageTable
+BootPageTable:
+    .long 0x00000083
+    .long 0x00400083
+    .long 0x00800083
+    .long 0x00C00083
+    .long 0x01000083
+    .long 0x01400083
+    .long 0x01800083
+    .long 0x01C00083
+    .long 0x02000083
+    .long 0x02400083
+	.rept (KERNEL_PAGE_NUMBER - 10)
+		.long 0
+	.endr
+    .long 0x00000083
+    .long 0x00400083
+    .long 0x00800083
+    .long 0x00C00083
+    .long 0x01000083
+    .long 0x01400083
+    .long 0x01800083
+    .long 0x01C00083
+    .long 0x02000083
+    .long 0x02400083
+	.rept (1024 - KERNEL_PAGE_NUMBER - 10)
+		.long 0
+	.endr

arch/i386/bootstrap/Multiboot/_start.s

@@ -0,0 +1,38 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.code32
+.extern Multiboot_start
+
+.section .bootstrap.text, "a"
+
+.global _start
+_start:
+	/* Check for multiboot */
+	cmp $0x2BADB002, %eax
+	je .Multiboot
+
+	/* Unkown bootloader */
+	.Hang:
+		cli
+		hlt
+		jmp .Hang
+
+	/* Multiboot */
+	.Multiboot:
+		call Multiboot_start
+		jmp .Hang

arch/i386/bootstrap/Multiboot/headers/header1.s

@@ -0,0 +1,27 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.intel_syntax noprefix
+
+.code32
+.section .multiboot, "a"
+.align 4
+
+MULTIBOOT_HEADER:
+	.long 0x1BADB002
+	.long 1 << 0 | 1 << 1
+	.long -(0x1BADB002 + (1 << 0 | 1 << 1))

arch/i386/bootstrap/Multiboot/headers/header2.s

@@ -0,0 +1,93 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.intel_syntax noprefix
+
+.code32
+.extern Multiboot_start
+
+/* https://www.gnu.org/software/grub/manual/multiboot2/multiboot.html */
+.section .multiboot2, "a"
+.align 0x1000
+MULTIBOOT2_HEADER_START:
+	.long 0xE85250D6
+	.long 0
+	.long (MULTIBOOT2_HEADER_END - MULTIBOOT2_HEADER_START)
+	.long 0x100000000 - (MULTIBOOT2_HEADER_END - MULTIBOOT2_HEADER_START) - 0 - 0xE85250D6
+.align 8
+InfoRequestTag_Start:
+	.word 1
+	.word 0
+	.long InfoRequestTag_End - InfoRequestTag_Start
+	.long 1 /* Command Line */
+	.long 2 /* Boot Loader Name */
+	.long 3 /* Module */
+	.long 4 /* Basic Memory Information */
+	.long 5 /* BIOS Boot Device */
+	.long 6 /* Memory Map */
+	.long 7 /* VBE */
+	.long 8 /* Framebuffer */
+	.long 9 /* ELF Sections */
+	.long 10 /* APM Table */
+	.long 11 /* EFI 32-bit System Table Pointer */
+	.long 12 /* EFI 64-bit System Table Pointer */
+	/* .long 13 */ /* SMBIOS */
+	.long 14 /* ACPI Old */
+	.long 15 /* ACPI New */
+	.long 16 /* Network */
+	.long 17 /* EFI Memory Map */
+	.long 18 /* EFI Boot Services Notifier */
+	.long 19 /* EFI 32-bit Image Handle Pointer */
+	.long 20 /* EFI 64-bit Image Handle Pointer */
+	.long 21 /* Load Base Address */
+InfoRequestTag_End:
+.align 8
+FramebufferTag_Start:
+	.word 5
+	.word 1
+	.long FramebufferTag_End - FramebufferTag_Start
+	.long 0
+	.long 0
+	.long 32
+FramebufferTag_End:
+.align 8
+EGATextSupportTag_Start:
+	.word 4
+	.word 0
+	.long EGATextSupportTag_End - EGATextSupportTag_Start
+	.long 0 /* https://www.gnu.org/software/grub/manual/multiboot2/html_node/Console-header-tags.html */
+EGATextSupportTag_End:
+.align 8
+AlignedModulesTag_Start:
+	.word 6
+	.word 0
+	.long AlignedModulesTag_End - AlignedModulesTag_Start
+AlignedModulesTag_End:
+.align 8
+EntryAddressTag_Start:
+	.word 3
+	.word 0
+	.long EntryAddressTag_End - EntryAddressTag_Start
+	.long Multiboot_start
+EntryAddressTag_End:
+.align 8
+EndTag_Start:
+	.word 0
+	.word 0
+	.long EndTag_End - EndTag_Start
+EndTag_End:
+MULTIBOOT2_HEADER_END:

arch/i386/bootstrap/Multiboot/helper/detect.s

@@ -0,0 +1,81 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.intel_syntax noprefix
+
+.code32
+.section .bootstrap.text, "a"
+
+.global DetectCPUID
+DetectCPUID:
+	pushfd
+	pop eax
+	mov ecx, eax
+	xor eax, 1 << 21
+	push eax
+	popfd
+	pushfd
+	pop eax
+	push ecx
+	popfd
+	xor eax, ecx
+	jz .NoCPUID
+	mov eax, 1
+	ret
+.NoCPUID:
+	xor eax, eax
+	ret
+
+.global Detect64Bit
+Detect64Bit:
+	mov eax, 0x80000000
+	cpuid
+	cmp eax, 0x80000001
+	jb .NoLongMode
+	mov eax, 0x80000001
+	cpuid
+	test edx, 1 << 29
+	jz .NoLongMode
+	mov eax, 1
+	ret
+.NoLongMode:
+	xor eax, eax
+	ret
+
+.global DetectPSE
+DetectPSE:
+	mov eax,  0x00000001
+	cpuid
+	test edx, 0x00000008
+	jz .NoPSE
+	mov eax, 1
+	ret
+.NoPSE:
+	xor eax, eax
+	ret
+
+.global DetectPAE
+DetectPAE:
+	mov eax,  0x00000001
+	cpuid
+	test edx, 0x00000040
+	jz .NoPAE
+	mov eax, 1
+	ret
+.NoPAE:
+	xor eax, eax
+	ret

arch/i386/bootstrap/Multiboot/helper/gdt32.s

@@ -0,0 +1,64 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.code32
+.section .bootstrap.text, "a"
+
+.align 32
+.global gdtr
+gdtr:
+	.word GDT32_END - GDT32 - 1
+	.long GDT32
+
+.align 32
+GDT32:
+	.quad 0x0
+
+	.word 0xFFFF
+	.word 0x0000
+	.byte 0x00
+	.word 0xCF9A
+	.byte 0x00
+
+	.word 0xFFFF
+	.word 0x0000
+	.byte 0x00
+	.word 0xCF92
+	.byte 0x00
+
+	.word 0x0100
+	.word 0x1000
+	.byte 0x00
+	.word 0x4092
+	.byte 0x00
+GDT32_END:
+	nop
+
+.global LoadGDT32
+LoadGDT32:
+	lgdt [gdtr]
+	ljmp $0x8, $ActivateGDT
+
+ActivateGDT:
+	mov $0x10, %cx
+	mov %cx, %ss
+	mov %cx, %ds
+	mov %cx, %es
+	mov %cx, %fs
+	mov $0x18, %cx
+	mov %cx, %gs
+	ret

arch/i386/bootstrap/Multiboot/mb1_parse.cpp

@@ -0,0 +1,210 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <types.h>
+
+#include <boot/protocol/multiboot.h>
+#include <memory.hpp>
+
+#include "../../../../kernel.h"
+
+void multiboot_parse(BootInfo &mb2binfo, uintptr_t Magic, uintptr_t Info)
+{
+	multiboot_info *InfoAddress = r_cst(multiboot_info *, Info);
+
+	if (InfoAddress->flags & MULTIBOOT_INFO_MEMORY)
+	{
+		fixme("mem_lower: %#x, mem_upper: %#x",
+			  InfoAddress->mem_lower, InfoAddress->mem_upper);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_BOOTDEV)
+	{
+		fixme("boot_device: %#x",
+			  InfoAddress->boot_device);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_CMDLINE)
+	{
+		strncpy(mb2binfo.Kernel.CommandLine,
+				r_cst(const char *, InfoAddress->cmdline),
+				strlen(r_cst(const char *, InfoAddress->cmdline)));
+		debug("Kernel command line: %s", mb2binfo.Kernel.CommandLine);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_MODS)
+	{
+		multiboot_mod_list *module = r_cst(multiboot_mod_list *, InfoAddress->mods_addr);
+		for (size_t i = 0; i < InfoAddress->mods_count; i++)
+		{
+			if (i > MAX_MODULES)
+			{
+				warn("Too many modules, skipping the rest...");
+				break;
+			}
+			mb2binfo.Modules[i].Address = (void *)(uint32_t)module[i].mod_start;
+			mb2binfo.Modules[i].Size = module[i].mod_end - module[i].mod_start;
+			strncpy(mb2binfo.Modules[i].Path, "(null)", 6);
+			strncpy(mb2binfo.Modules[i].CommandLine, r_cst(const char *, module[i].cmdline),
+					strlen(r_cst(const char *, module[i].cmdline)));
+			debug("Module: %s", mb2binfo.Modules[i].Path);
+		}
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_AOUT_SYMS)
+	{
+		fixme("aout_sym: [tabsize: %#x, strsize: %#x, addr: %#x, reserved: %#x]",
+			  InfoAddress->u.aout_sym.tabsize, InfoAddress->u.aout_sym.strsize,
+			  InfoAddress->u.aout_sym.addr, InfoAddress->u.aout_sym.reserved);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_ELF_SHDR)
+	{
+		mb2binfo.Kernel.Symbols.Num = InfoAddress->u.elf_sec.num;
+		mb2binfo.Kernel.Symbols.EntSize = InfoAddress->u.elf_sec.size;
+		mb2binfo.Kernel.Symbols.Shndx = InfoAddress->u.elf_sec.shndx;
+		mb2binfo.Kernel.Symbols.Sections = s_cst(uintptr_t, InfoAddress->u.elf_sec.addr);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_MEM_MAP)
+	{
+		mb2binfo.Memory.Entries = InfoAddress->mmap_length / sizeof(multiboot_mmap_entry);
+		for (uint32_t i = 0; i < mb2binfo.Memory.Entries; i++)
+		{
+			if (i > MAX_MEMORY_ENTRIES)
+			{
+				warn("Too many memory entries, skipping the rest...");
+				break;
+			}
+			multiboot_mmap_entry entry = r_cst(multiboot_mmap_entry *, InfoAddress->mmap_addr)[i];
+			mb2binfo.Memory.Size += (__SIZE_TYPE__)entry.len;
+			switch (entry.type)
+			{
+			case MULTIBOOT_MEMORY_AVAILABLE:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = Usable;
+				break;
+			case MULTIBOOT_MEMORY_RESERVED:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = Reserved;
+				break;
+			case MULTIBOOT_MEMORY_ACPI_RECLAIMABLE:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = ACPIReclaimable;
+				break;
+			case MULTIBOOT_MEMORY_NVS:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = ACPINVS;
+				break;
+			case MULTIBOOT_MEMORY_BADRAM:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = BadMemory;
+				break;
+			default:
+				mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+				mb2binfo.Memory.Entry[i].Length = (__SIZE_TYPE__)entry.len;
+				mb2binfo.Memory.Entry[i].Type = Unknown;
+				break;
+			}
+			debug("Memory entry: [BaseAddress: %#x, Length: %#x, Type: %d]",
+				  mb2binfo.Memory.Entry[i].BaseAddress,
+				  mb2binfo.Memory.Entry[i].Length,
+				  mb2binfo.Memory.Entry[i].Type);
+		}
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_DRIVE_INFO)
+	{
+		fixme("drives_length: %d, drives_addr: %#x",
+			  InfoAddress->drives_length, InfoAddress->drives_addr);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_CONFIG_TABLE)
+	{
+		fixme("config_table: %#x",
+			  InfoAddress->config_table);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_BOOT_LOADER_NAME)
+	{
+		strncpy(mb2binfo.Bootloader.Name,
+				r_cst(const char *, InfoAddress->boot_loader_name),
+				strlen(r_cst(const char *, InfoAddress->boot_loader_name)));
+		debug("Bootloader name: %s", mb2binfo.Bootloader.Name);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_APM_TABLE)
+	{
+		fixme("apm_table: %#x",
+			  InfoAddress->apm_table);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_VBE_INFO)
+	{
+		fixme("vbe_control_info: %#x, vbe_mode_info: %#x, vbe_mode: %#x, vbe_interface_seg: %#x, vbe_interface_off: %#x, vbe_interface_len: %#x",
+			  InfoAddress->vbe_control_info, InfoAddress->vbe_mode_info,
+			  InfoAddress->vbe_mode, InfoAddress->vbe_interface_seg,
+			  InfoAddress->vbe_interface_off, InfoAddress->vbe_interface_len);
+	}
+	if (InfoAddress->flags & MULTIBOOT_INFO_FRAMEBUFFER_INFO)
+	{
+		static int fb_count = 0;
+		mb2binfo.Framebuffer[fb_count].BaseAddress = (void *)InfoAddress->framebuffer_addr;
+		mb2binfo.Framebuffer[fb_count].Width = InfoAddress->framebuffer_width;
+		mb2binfo.Framebuffer[fb_count].Height = InfoAddress->framebuffer_height;
+		mb2binfo.Framebuffer[fb_count].Pitch = InfoAddress->framebuffer_pitch;
+		mb2binfo.Framebuffer[fb_count].BitsPerPixel = InfoAddress->framebuffer_bpp;
+		switch (InfoAddress->framebuffer_type)
+		{
+		case MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED:
+		{
+			mb2binfo.Framebuffer[fb_count].Type = Indexed;
+			break;
+		}
+		case MULTIBOOT_FRAMEBUFFER_TYPE_RGB:
+		{
+			mb2binfo.Framebuffer[fb_count].Type = RGB;
+			mb2binfo.Framebuffer[fb_count].RedMaskSize = InfoAddress->framebuffer_red_mask_size;
+			mb2binfo.Framebuffer[fb_count].RedMaskShift = InfoAddress->framebuffer_red_field_position;
+			mb2binfo.Framebuffer[fb_count].GreenMaskSize = InfoAddress->framebuffer_green_mask_size;
+			mb2binfo.Framebuffer[fb_count].GreenMaskShift = InfoAddress->framebuffer_green_field_position;
+			mb2binfo.Framebuffer[fb_count].BlueMaskSize = InfoAddress->framebuffer_blue_mask_size;
+			mb2binfo.Framebuffer[fb_count].BlueMaskShift = InfoAddress->framebuffer_blue_field_position;
+			break;
+		}
+		case MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT:
+		{
+			mb2binfo.Framebuffer[fb_count].Type = EGA;
+			break;
+		}
+		default:
+		{
+			mb2binfo.Framebuffer[fb_count].Type = Unknown_Framebuffer_Type;
+			break;
+		}
+		}
+		debug("Framebuffer %d: %dx%d %d bpp",
+			  fb_count, InfoAddress->framebuffer_width,
+			  InfoAddress->framebuffer_height,
+			  InfoAddress->framebuffer_bpp);
+		debug("More info:\nAddress: %p\nPitch: %d\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
+			  InfoAddress->framebuffer_addr, InfoAddress->framebuffer_pitch, InfoAddress->framebuffer_type,
+			  InfoAddress->framebuffer_red_mask_size, InfoAddress->framebuffer_red_field_position, InfoAddress->framebuffer_green_mask_size,
+			  InfoAddress->framebuffer_green_field_position, InfoAddress->framebuffer_blue_mask_size, InfoAddress->framebuffer_blue_field_position);
+	}
+
+	mb2binfo.Kernel.PhysicalBase = (void *)&_bootstrap_start;
+	mb2binfo.Kernel.VirtualBase = (void *)(uint32_t)((uint32_t)&_bootstrap_start + 0xC0000000);
+	mb2binfo.Kernel.Size = ((uint32_t)&_kernel_end - (uint32_t)&_kernel_start) + ((uint32_t)&_bootstrap_end - (uint32_t)&_bootstrap_start);
+	debug("Kernel base: %p (physical) %p (virtual)", mb2binfo.Kernel.PhysicalBase, mb2binfo.Kernel.VirtualBase);
+
+	Entry(&mb2binfo);
+}

arch/i386/bootstrap/Multiboot/mb2_parse.cpp

@@ -0,0 +1,300 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <types.h>
+
+#include <memory.hpp>
+
+#include <boot/protocol/multiboot2.h>
+#include "../../../../kernel.h"
+
+void multiboot2_parse(BootInfo &mb2binfo, uintptr_t Magic, uintptr_t Info)
+{
+	if (Info == NULL || Magic == NULL)
+	{
+		if (Magic == NULL)
+			error("Multiboot magic is NULL");
+		if (Info == NULL)
+			error("Multiboot info is NULL");
+		CPU::Stop();
+	}
+	else if (Magic != MULTIBOOT2_BOOTLOADER_MAGIC)
+	{
+		error("Multiboot magic is invalid (%#x != %#x)", Magic, MULTIBOOT2_BOOTLOADER_MAGIC);
+		CPU::Stop();
+	}
+
+	{
+		auto InfoAddress = Info;
+		for (auto Tag = (struct multiboot_tag *)((uint8_t *)InfoAddress + 8);
+			 ;
+			 Tag = (struct multiboot_tag *)((multiboot_uint8_t *)Tag + ((Tag->size + 7) & ~7)))
+		{
+			if (Tag->type == MULTIBOOT_TAG_TYPE_END)
+			{
+				debug("End of multiboot2 tags");
+				break;
+			}
+
+			switch (Tag->type)
+			{
+			case MULTIBOOT_TAG_TYPE_CMDLINE:
+			{
+				strncpy(mb2binfo.Kernel.CommandLine,
+						((multiboot_tag_string *)Tag)->string,
+						strlen(((multiboot_tag_string *)Tag)->string));
+				debug("Kernel command line: %s", mb2binfo.Kernel.CommandLine);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_BOOT_LOADER_NAME:
+			{
+				strncpy(mb2binfo.Bootloader.Name,
+						((multiboot_tag_string *)Tag)->string,
+						strlen(((multiboot_tag_string *)Tag)->string));
+				debug("Bootloader name: %s", mb2binfo.Bootloader.Name);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_MODULE:
+			{
+				multiboot_tag_module *module = (multiboot_tag_module *)Tag;
+				static int module_count = 0;
+				mb2binfo.Modules[module_count].Address = (void *)(uint32_t)module->mod_start;
+				mb2binfo.Modules[module_count].Size = module->mod_end - module->mod_start;
+				strncpy(mb2binfo.Modules[module_count].Path, "(null)", 6);
+				strncpy(mb2binfo.Modules[module_count].CommandLine, module->cmdline,
+						strlen(module->cmdline));
+				debug("Module: %s", mb2binfo.Modules[module_count].Path);
+				module_count++;
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_BASIC_MEMINFO:
+			{
+				multiboot_tag_basic_meminfo *meminfo = (multiboot_tag_basic_meminfo *)Tag;
+				fixme("basic_meminfo->[mem_lower: %#x, mem_upper: %#x]",
+					  meminfo->mem_lower, meminfo->mem_upper);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_BOOTDEV:
+			{
+				multiboot_tag_bootdev *bootdev = (multiboot_tag_bootdev *)Tag;
+				fixme("bootdev->[biosdev: %#x, slice: %#x, part: %#x]",
+					  bootdev->biosdev, bootdev->slice, bootdev->part);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_MMAP:
+			{
+				multiboot_tag_mmap *mmap = (multiboot_tag_mmap *)Tag;
+				size_t EntryCount = mmap->size / sizeof(multiboot_mmap_entry);
+				mb2binfo.Memory.Entries = EntryCount;
+				for (uint32_t i = 0; i < EntryCount; i++)
+				{
+					if (i > MAX_MEMORY_ENTRIES)
+					{
+						warn("Too many memory entries, skipping the rest...");
+						break;
+					}
+					multiboot_mmap_entry entry = mmap->entries[i];
+					mb2binfo.Memory.Size += (size_t)entry.len;
+					switch (entry.type)
+					{
+					case MULTIBOOT_MEMORY_AVAILABLE:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = Usable;
+						break;
+					case MULTIBOOT_MEMORY_RESERVED:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = Reserved;
+						break;
+					case MULTIBOOT_MEMORY_ACPI_RECLAIMABLE:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = ACPIReclaimable;
+						break;
+					case MULTIBOOT_MEMORY_NVS:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = ACPINVS;
+						break;
+					case MULTIBOOT_MEMORY_BADRAM:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = BadMemory;
+						break;
+					default:
+						mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
+						mb2binfo.Memory.Entry[i].Length = (size_t)entry.len;
+						mb2binfo.Memory.Entry[i].Type = Unknown;
+						break;
+					}
+					debug("Memory entry: [BaseAddress: %#x, Length: %#x, Type: %d]",
+						  mb2binfo.Memory.Entry[i].BaseAddress,
+						  mb2binfo.Memory.Entry[i].Length,
+						  mb2binfo.Memory.Entry[i].Type);
+				}
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_VBE:
+			{
+				multiboot_tag_vbe *vbe = (multiboot_tag_vbe *)Tag;
+				fixme("vbe->[vbe_mode: %#x, vbe_interface_seg: %#x, vbe_interface_off: %#x, vbe_interface_len: %#x]",
+					  vbe->vbe_mode, vbe->vbe_interface_seg, vbe->vbe_interface_off, vbe->vbe_interface_len);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_FRAMEBUFFER:
+			{
+				multiboot_tag_framebuffer *fb = (multiboot_tag_framebuffer *)Tag;
+				static int fb_count = 0;
+				mb2binfo.Framebuffer[fb_count].BaseAddress = (void *)fb->common.framebuffer_addr;
+				mb2binfo.Framebuffer[fb_count].Width = fb->common.framebuffer_width;
+				mb2binfo.Framebuffer[fb_count].Height = fb->common.framebuffer_height;
+				mb2binfo.Framebuffer[fb_count].Pitch = fb->common.framebuffer_pitch;
+				mb2binfo.Framebuffer[fb_count].BitsPerPixel = fb->common.framebuffer_bpp;
+				switch (fb->common.framebuffer_type)
+				{
+				case MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED:
+				{
+					mb2binfo.Framebuffer[fb_count].Type = Indexed;
+					break;
+				}
+				case MULTIBOOT_FRAMEBUFFER_TYPE_RGB:
+				{
+					mb2binfo.Framebuffer[fb_count].Type = RGB;
+					mb2binfo.Framebuffer[fb_count].RedMaskSize = fb->framebuffer_red_mask_size;
+					mb2binfo.Framebuffer[fb_count].RedMaskShift = fb->framebuffer_red_field_position;
+					mb2binfo.Framebuffer[fb_count].GreenMaskSize = fb->framebuffer_green_mask_size;
+					mb2binfo.Framebuffer[fb_count].GreenMaskShift = fb->framebuffer_green_field_position;
+					mb2binfo.Framebuffer[fb_count].BlueMaskSize = fb->framebuffer_blue_mask_size;
+					mb2binfo.Framebuffer[fb_count].BlueMaskShift = fb->framebuffer_blue_field_position;
+					break;
+				}
+				case MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT:
+				{
+					mb2binfo.Framebuffer[fb_count].Type = EGA;
+					break;
+				}
+				default:
+				{
+					mb2binfo.Framebuffer[fb_count].Type = Unknown_Framebuffer_Type;
+					break;
+				}
+				}
+				debug("Framebuffer %d: %dx%d %d bpp", fb_count, fb->common.framebuffer_width, fb->common.framebuffer_height, fb->common.framebuffer_bpp);
+				debug("More info:\nAddress: %p\nPitch: %d\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
+					  fb->common.framebuffer_addr, fb->common.framebuffer_pitch, fb->common.framebuffer_type,
+					  fb->framebuffer_red_mask_size, fb->framebuffer_red_field_position, fb->framebuffer_green_mask_size,
+					  fb->framebuffer_green_field_position, fb->framebuffer_blue_mask_size, fb->framebuffer_blue_field_position);
+				fb_count++;
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_ELF_SECTIONS:
+			{
+				multiboot_tag_elf_sections *elf = (multiboot_tag_elf_sections *)Tag;
+				mb2binfo.Kernel.Symbols.Num = elf->num;
+				mb2binfo.Kernel.Symbols.EntSize = elf->entsize;
+				mb2binfo.Kernel.Symbols.Shndx = elf->shndx;
+				mb2binfo.Kernel.Symbols.Sections = (uintptr_t)&elf->sections;
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_APM:
+			{
+				multiboot_tag_apm *apm = (multiboot_tag_apm *)Tag;
+				fixme("apm->[version: %d, cseg: %d, offset: %d, cseg_16: %d, dseg: %d, flags: %d, cseg_len: %d, cseg_16_len: %d, dseg_len: %d]",
+					  apm->version, apm->cseg, apm->offset, apm->cseg_16, apm->dseg, apm->flags, apm->cseg_len, apm->cseg_16_len, apm->dseg_len);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI32:
+			{
+				multiboot_tag_efi32 *efi32 = (multiboot_tag_efi32 *)Tag;
+				fixme("efi32->[pointer: %p, size: %d]", efi32->pointer, efi32->size);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI64:
+			{
+				multiboot_tag_efi64 *efi64 = (multiboot_tag_efi64 *)Tag;
+				fixme("efi64->[pointer: %p, size: %d]", efi64->pointer, efi64->size);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_SMBIOS:
+			{
+				multiboot_tag_smbios *smbios = (multiboot_tag_smbios *)Tag;
+				fixme("smbios->[major: %d, minor: %d]", smbios->major, smbios->minor);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_ACPI_OLD:
+			{
+				mb2binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_old_acpi *)Tag)->rsdp;
+				debug("OLD ACPI RSDP: %p", mb2binfo.RSDP);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_ACPI_NEW:
+			{
+				mb2binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_new_acpi *)Tag)->rsdp;
+				debug("NEW ACPI RSDP: %p", mb2binfo.RSDP);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_NETWORK:
+			{
+				multiboot_tag_network *net = (multiboot_tag_network *)Tag;
+				fixme("network->[dhcpack: %p]", net->dhcpack);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI_MMAP:
+			{
+				multiboot_tag_efi_mmap *efi_mmap = (multiboot_tag_efi_mmap *)Tag;
+				fixme("efi_mmap->[descr_size: %d, descr_vers: %d, efi_mmap: %p]",
+					  efi_mmap->descr_size, efi_mmap->descr_vers, efi_mmap->efi_mmap);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI_BS:
+			{
+				fixme("efi_bs->[%p] (unknown structure)", Tag);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI32_IH:
+			{
+				multiboot_tag_efi32_ih *efi32_ih = (multiboot_tag_efi32_ih *)Tag;
+				fixme("efi32_ih->[pointer: %p]", efi32_ih->pointer);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_EFI64_IH:
+			{
+				multiboot_tag_efi64_ih *efi64_ih = (multiboot_tag_efi64_ih *)Tag;
+				fixme("efi64_ih->[pointer: %p]", efi64_ih->pointer);
+				break;
+			}
+			case MULTIBOOT_TAG_TYPE_LOAD_BASE_ADDR:
+			{
+				multiboot_tag_load_base_addr *load_base_addr = (multiboot_tag_load_base_addr *)Tag;
+				mb2binfo.Kernel.PhysicalBase = (void *)(uint32_t)load_base_addr->load_base_addr;
+				mb2binfo.Kernel.VirtualBase = (void *)(uint32_t)(load_base_addr->load_base_addr + 0xC0000000);
+				mb2binfo.Kernel.Size = (size_t)(((uint32_t)&_kernel_end - (uint32_t)&_kernel_start) + ((uint32_t)&_bootstrap_end - (uint32_t)&_bootstrap_start));
+				debug("Kernel base: %p (physical) %p (virtual)", mb2binfo.Kernel.PhysicalBase, mb2binfo.Kernel.VirtualBase);
+				break;
+			}
+			default:
+			{
+				error("Unknown multiboot2 tag type: %d", Tag->type);
+				break;
+			}
+			}
+		}
+	}
+
+	Entry(&mb2binfo);
+}

arch/i386/bootstrap/Multiboot/multiboot.cpp

@@ -0,0 +1,53 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <types.h>
+
+#include <memory.hpp>
+
+#include "../../../../kernel.h"
+
+#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
+#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
+#define MULTIBOOT2_HEADER_MAGIC 0xe85250d6
+#define MULTIBOOT2_BOOTLOADER_MAGIC 0x36d76289
+
+void multiboot_parse(BootInfo &mb2binfo, uintptr_t Magic, uintptr_t Info);
+void multiboot2_parse(BootInfo &mb2binfo, uintptr_t Magic, uintptr_t Info);
+
+EXTERNC void multiboot_main(uintptr_t Magic, uintptr_t Info)
+{
+	BootInfo mb2binfo{};
+
+	if (Info == NULL || Magic == NULL)
+	{
+		if (Magic == NULL)
+			error("Multiboot magic is NULL");
+		if (Info == NULL)
+			error("Multiboot info is NULL");
+		CPU::Stop();
+	}
+	else if (Magic == MULTIBOOT_BOOTLOADER_MAGIC)
+		multiboot_parse(mb2binfo, Magic, Info);
+	else if (Magic == MULTIBOOT2_BOOTLOADER_MAGIC)
+		multiboot2_parse(mb2binfo, Magic, Info);
+	else
+	{
+		error("Unknown multiboot magic %#x", Magic);
+		CPU::Stop();
+	}
+}

arch/i386/bootstrap/Multiboot/start.s

@@ -0,0 +1,79 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+.code32
+KERNEL_STACK_SIZE = 0x4000 /* 16KB */
+
+.extern DetectCPUID
+.extern DetectPSE
+.extern multiboot_main
+.extern LoadGDT32
+.extern BootPageTable
+
+.section .bootstrap.data, "a"
+MB_HeaderMagic:
+	.quad 0
+
+MB_HeaderInfo:
+	.quad 0
+
+.section .bootstrap.text, "a"
+
+.global Multiboot_start
+Multiboot_start:
+	cli
+
+	mov %eax, [MB_HeaderMagic]
+	mov %ebx, [MB_HeaderInfo]
+
+	call DetectCPUID
+	cmp $0, %eax
+	je .
+
+	call DetectPSE
+	cmp $0, %eax
+	je .
+
+	mov %cr4, %ecx
+	or $0x00000010, %ecx /* PSE */
+	mov %ecx, %cr4
+
+	call LoadGDT32
+
+	mov $BootPageTable, %ecx
+	mov %ecx, %cr3
+
+	mov %cr0, %ecx
+	or $0x80000000, %ecx /* PG */
+	mov %ecx, %cr0
+
+	mov $(KernelStack + KERNEL_STACK_SIZE), %esp
+	mov $0x0, %ebp
+
+	mov [MB_HeaderMagic], %eax
+	mov [MB_HeaderInfo], %ebx
+	push %ebx
+	push %eax
+	call multiboot_main
+.Hang:
+	hlt
+	jmp .Hang
+
+.section .bootstrap.bss, "a"
+.align 16
+KernelStack:
+	.space KERNEL_STACK_SIZE

arch/i386/cpu/apic.cpp

@@ -0,0 +1,411 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include "apic.hpp"
+
+#include <memory.hpp>
+#include <uart.hpp>
+#include <lock.hpp>
+#include <acpi.hpp>
+#include <cpu.hpp>
+#include <smp.hpp>
+#include <io.h>
+
+#include "../../../kernel.h"
+
+NewLock(APICLock);
+
+using namespace CPU::x32;
+using namespace CPU::x86;
+
+/*
+In constructor ‘APIC::APIC::APIC(int)’:
+warning: left shift count >= width of type
+|         APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
+|                                                          ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
+*/
+#pragma GCC diagnostic ignored "-Wshift-count-overflow"
+
+namespace APIC
+{
+	// headache
+	// https://www.amd.com/system/files/TechDocs/24593.pdf
+	// https://www.naic.edu/~phil/software/intel/318148.pdf
+
+	uint32_t APIC::Read(uint32_t Register)
+	{
+#ifdef DEBUG
+		if (Register != APIC_ICRLO &&
+			Register != APIC_ICRHI &&
+			Register != APIC_ID)
+			debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
+#endif
+		if (x2APICSupported)
+		{
+			if (Register != APIC_ICRHI)
+				return s_cst(uint32_t, rdmsr((Register >> 4) + 0x800));
+			else
+				return s_cst(uint32_t, rdmsr(0x30 + 0x800));
+		}
+		else
+		{
+			CPU::MemBar::Barrier();
+			uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
+			CPU::MemBar::Barrier();
+			return ret;
+		}
+	}
+
+	void APIC::Write(uint32_t Register, uint32_t Value)
+	{
+#ifdef DEBUG
+		if (Register != APIC_EOI &&
+			Register != APIC_TDCR &&
+			Register != APIC_TIMER &&
+			Register != APIC_TICR &&
+			Register != APIC_ICRLO &&
+			Register != APIC_ICRHI)
+			debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
+#endif
+		if (x2APICSupported)
+		{
+			if (Register != APIC_ICRHI)
+				wrmsr((Register >> 4) + 0x800, Value);
+			else
+				wrmsr(MSR_X2APIC_ICR, Value);
+		}
+		else
+		{
+			CPU::MemBar::Barrier();
+			*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
+			CPU::MemBar::Barrier();
+		}
+	}
+
+	void APIC::IOWrite(uint64_t Base, uint32_t Register, uint32_t Value)
+	{
+		debug("APIC::IOWrite(%#lx, %#lx, %#lx)", Base, Register, Value);
+		CPU::MemBar::Barrier();
+		*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
+		CPU::MemBar::Barrier();
+		*((volatile uint32_t *)(((uintptr_t)Base + 16))) = Value;
+		CPU::MemBar::Barrier();
+	}
+
+	uint32_t APIC::IORead(uint64_t Base, uint32_t Register)
+	{
+		debug("APIC::IORead(%#lx, %#lx)", Base, Register);
+		CPU::MemBar::Barrier();
+		*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
+		CPU::MemBar::Barrier();
+		uint32_t ret = *((volatile uint32_t *)(((uintptr_t)Base + 16)));
+		CPU::MemBar::Barrier();
+		return ret;
+	}
+
+	void APIC::EOI() { this->Write(APIC_EOI, 0); }
+
+	void APIC::WaitForIPI()
+	{
+		InterruptCommandRegisterLow icr = {.raw = 0};
+		do
+		{
+			icr.raw = this->Read(APIC_ICRLO);
+			CPU::Pause();
+		} while (icr.DeliveryStatus != Idle);
+	}
+
+	void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr)
+	{
+		SmartCriticalSection(APICLock);
+		if (x2APICSupported)
+		{
+			wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+		else
+		{
+			this->Write(APIC_ICRHI, (CPU << 24));
+			this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+	}
+
+	void APIC::SendInitIPI(uint8_t CPU)
+	{
+		SmartCriticalSection(APICLock);
+		if (x2APICSupported)
+		{
+			InterruptCommandRegisterLow icr = {.raw = 0};
+			icr.DeliveryMode = INIT;
+			icr.Level = Assert;
+			wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+		else
+		{
+			InterruptCommandRegisterLow icr = {.raw = 0};
+			icr.DeliveryMode = INIT;
+			icr.Level = Assert;
+			this->Write(APIC_ICRHI, (CPU << 24));
+			this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+	}
+
+	void APIC::SendStartupIPI(uint8_t CPU, uint64_t StartupAddress)
+	{
+		SmartCriticalSection(APICLock);
+		if (x2APICSupported)
+		{
+			InterruptCommandRegisterLow icr = {.raw = 0};
+			icr.Vector = s_cst(uint8_t, StartupAddress >> 12);
+			icr.DeliveryMode = Startup;
+			icr.Level = Assert;
+			wrmsr(MSR_X2APIC_ICR, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+		else
+		{
+			InterruptCommandRegisterLow icr = {.raw = 0};
+			icr.Vector = s_cst(uint8_t, StartupAddress >> 12);
+			icr.DeliveryMode = Startup;
+			icr.Level = Assert;
+			this->Write(APIC_ICRHI, (CPU << 24));
+			this->Write(APIC_ICRLO, s_cst(uint32_t, icr.raw));
+			this->WaitForIPI();
+		}
+	}
+
+	uint32_t APIC::IOGetMaxRedirect(uint32_t APICID)
+	{
+		uint32_t TableAddress = (this->IORead((((ACPI::MADT *)PowerManager->GetMADT())->ioapic[APICID]->Address), GetIOAPICVersion));
+		return ((IOAPICVersion *)&TableAddress)->MaximumRedirectionEntry;
+	}
+
+	void APIC::RawRedirectIRQ(uint16_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status)
+	{
+		uint64_t Value = Vector;
+
+		int64_t IOAPICTarget = -1;
+		for (uint64_t i = 0; ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)] != 0; i++)
+			if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)]->GSIBase <= GSI)
+				if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(i)]->GSIBase + IOGetMaxRedirect(s_cst(uint32_t, i)) > GSI)
+				{
+					IOAPICTarget = i;
+					break;
+				}
+
+		if (IOAPICTarget == -1)
+		{
+			error("No ISO table found for I/O APIC");
+			return;
+		}
+
+		// TODO: IOAPICRedirectEntry Entry = {.raw = 0};
+
+		if (Flags & ActiveHighLow)
+			Value |= (1 << 13);
+
+		if (Flags & EdgeLevel)
+			Value |= (1 << 15);
+
+		if (!Status)
+			Value |= (1 << 16);
+
+		Value |= (((uintptr_t)CPU) << 56);
+		uint32_t IORegister = (GSI - ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->GSIBase) * 2 + 16;
+
+		this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->Address,
+					  IORegister, (uint32_t)Value);
+		this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[std::size_t(IOAPICTarget)]->Address,
+					  IORegister + 1, (uint32_t)(Value >> 32));
+	}
+
+	void APIC::RedirectIRQ(int CPU, uint16_t IRQ, int Status)
+	{
+		for (uint64_t i = 0; i < ((ACPI::MADT *)PowerManager->GetMADT())->iso.size(); i++)
+			if (((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource == IRQ)
+			{
+				debug("[ISO %d] Mapping to source IRQ%#d GSI:%#lx on CPU %d",
+					  i, ((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource,
+					  ((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->GSI,
+					  CPU);
+
+				this->RawRedirectIRQ(((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->IRQSource + 0x20,
+									 ((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->GSI,
+									 ((ACPI::MADT *)PowerManager->GetMADT())->iso[std::size_t(i)]->Flags,
+									 CPU, Status);
+				return;
+			}
+		debug("Mapping IRQ%d on CPU %d", IRQ, CPU);
+		this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
+	}
+
+	void APIC::RedirectIRQs(int CPU)
+	{
+		SmartCriticalSection(APICLock);
+		debug("Redirecting IRQs...");
+		for (uint8_t i = 0; i < 16; i++)
+			this->RedirectIRQ(CPU, i, 1);
+		debug("Redirecting IRQs completed.");
+	}
+
+	APIC::APIC(int Core)
+	{
+		SmartCriticalSection(APICLock);
+		APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
+		uint64_t BaseLow = BaseStruct.ApicBaseLo;
+		uint64_t BaseHigh = BaseStruct.ApicBaseHi;
+		this->APICBaseAddress = BaseLow << 12u | BaseHigh << 32u;
+		trace("APIC Address: %#lx", this->APICBaseAddress);
+		Memory::Virtual().Map((void *)this->APICBaseAddress, (void *)this->APICBaseAddress, Memory::PTFlag::RW | Memory::PTFlag::PCD);
+
+		bool x2APICSupported = false;
+		if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
+		{
+			CPU::x86::AMD::CPUID0x00000001 cpuid;
+			cpuid.Get();
+			if (cpuid.ECX.x2APIC)
+			{
+				// x2APICSupported = cpuid.ECX.x2APIC;
+				fixme("x2APIC is supported");
+			}
+		}
+		else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
+		{
+			CPU::x86::Intel::CPUID0x00000001 cpuid;
+			cpuid.Get();
+			if (cpuid.ECX.x2APIC)
+			{
+				// x2APICSupported = cpuid.ECX.x2APIC;
+				fixme("x2APIC is supported");
+			}
+		}
+
+		if (x2APICSupported)
+		{
+			this->x2APICSupported = true;
+			wrmsr(MSR_APIC_BASE, (rdmsr(MSR_APIC_BASE) | (1 << 11)) & ~(1 << 10));
+			BaseStruct.EN = 1;
+			wrmsr(MSR_APIC_BASE, BaseStruct.raw);
+		}
+		else
+		{
+			BaseStruct.EN = 1;
+			wrmsr(MSR_APIC_BASE, BaseStruct.raw);
+		}
+
+		this->Write(APIC_TPR, 0x0);
+		// this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
+
+		if (!this->x2APICSupported)
+		{
+			this->Write(APIC_DFR, 0xF0000000);
+			this->Write(APIC_LDR, this->Read(APIC_ID));
+		}
+
+		ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
+
+		for (size_t i = 0; i < madt->nmi.size(); i++)
+		{
+			if (madt->nmi[std::size_t(i)]->processor != 0xFF && Core != madt->nmi[std::size_t(i)]->processor)
+				return;
+
+			uint32_t nmi = 0x402;
+			if (madt->nmi[std::size_t(i)]->flags & 2)
+				nmi |= 1 << 13;
+			if (madt->nmi[std::size_t(i)]->flags & 8)
+				nmi |= 1 << 15;
+			if (madt->nmi[std::size_t(i)]->lint == 0)
+				this->Write(APIC_LINT0, nmi);
+			else if (madt->nmi[std::size_t(i)]->lint == 1)
+				this->Write(APIC_LINT1, nmi);
+		}
+
+		// Setup the spurrious interrupt vector
+		Spurious Spurious = {.raw = this->Read(APIC_SVR)};
+		Spurious.Vector = IRQ223; // TODO: Should I map the IRQ to something?
+		Spurious.Software = 1;
+		this->Write(APIC_SVR, s_cst(uint32_t, Spurious.raw));
+
+		static int once = 0;
+		if (!once++)
+		{
+			// Disable PIT
+			outb(0x43, 0x28);
+			outb(0x40, 0x0);
+
+			// Disable PIC
+			outb(0x21, 0xFF);
+			outb(0xA1, 0xFF);
+		}
+	}
+
+	APIC::~APIC() {}
+
+	void Timer::OnInterruptReceived(TrapFrame *Frame) { UNUSED(Frame); }
+
+	void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
+	{
+		SmartCriticalSection(APICLock);
+		LVTTimer timer = {.raw = 0};
+		timer.Vector = s_cst(uint8_t, Vector);
+		timer.TimerMode = 0;
+		if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
+			this->lapic->Write(APIC_TDCR, DivideBy128);
+		else
+			this->lapic->Write(APIC_TDCR, DivideBy16);
+		this->lapic->Write(APIC_TICR, s_cst(uint32_t, Ticks * Miliseconds));
+		this->lapic->Write(APIC_TIMER, s_cst(uint32_t, timer.raw));
+	}
+
+	Timer::Timer(APIC *apic) : Interrupts::Handler(0) /* IRQ0 */
+	{
+		SmartCriticalSection(APICLock);
+		this->lapic = apic;
+		LVTTimerDivide Divider = DivideBy16;
+
+		trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
+
+		this->lapic->Write(APIC_TDCR, Divider);
+		this->lapic->Write(APIC_TICR, 0xFFFFFFFF);
+
+		TimeManager->Sleep(1, Time::Units::Milliseconds);
+
+		// Mask the timer
+		this->lapic->Write(APIC_TIMER, 0x10000 /* LVTTimer.Mask flag */);
+		Ticks = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
+
+		// Config for IRQ0 timer
+		LVTTimer timer = {.raw = 0};
+		timer.Vector = IRQ0;
+		timer.Mask = Unmasked;
+		timer.TimerMode = LVTTimerMode::OneShot;
+
+		// Initialize APIC timer
+		this->lapic->Write(APIC_TDCR, Divider);
+		this->lapic->Write(APIC_TICR, s_cst(uint32_t, Ticks));
+		this->lapic->Write(APIC_TIMER, s_cst(uint32_t, timer.raw));
+		trace("%d APIC Timer %d ticks in.", GetCurrentCPU()->ID, Ticks);
+		KPrint("APIC Timer: \e8888FF%ld\eCCCCCC ticks.", Ticks);
+	}
+
+	Timer::~Timer()
+	{
+	}
+}

arch/i386/cpu/apic.hpp

@@ -0,0 +1,356 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#ifndef __FENNIX_KERNEL_APIC_H__
+#define __FENNIX_KERNEL_APIC_H__
+
+#include <types.h>
+
+#include <ints.hpp>
+#include <cpu.hpp>
+
+namespace APIC
+{
+	enum APICRegisters
+	{
+		// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
+		APIC_ID = 0x20,       // Local APIC ID
+		APIC_VER = 0x30,      // Local APIC Version
+		APIC_TPR = 0x80,      // Task Priority
+		APIC_APR = 0x90,      // Arbitration Priority
+		APIC_PPR = 0xA0,      // Processor Priority
+		APIC_EOI = 0xB0,      // EOI
+		APIC_RRD = 0xC0,      // Remote Read
+		APIC_LDR = 0xD0,      // Logical Destination
+		APIC_DFR = 0xE0,      // Destination Format
+		APIC_SVR = 0xF0,      // Spurious Interrupt Vector
+		APIC_ISR = 0x100,     // In-Service (8 registers)
+		APIC_TMR = 0x180,     // Trigger Mode (8 registers)
+		APIC_IRR = 0x200,     // Interrupt Request (8 registers)
+		APIC_ESR = 0x280,     // Error Status
+		APIC_ICRLO = 0x300,   // Interrupt Command
+		APIC_ICRHI = 0x310,   // Interrupt Command [63:32]
+		APIC_TIMER = 0x320,   // LVT Timer
+		APIC_THERMAL = 0x330, // LVT Thermal Sensor
+		APIC_PERF = 0x340,    // LVT Performance Counter
+		APIC_LINT0 = 0x350,   // LVT LINT0
+		APIC_LINT1 = 0x360,   // LVT LINT1
+		APIC_ERROR = 0x370,   // LVT Error
+		APIC_TICR = 0x380,    // Initial Count (for Timer)
+		APIC_TCCR = 0x390,    // Current Count (for Timer)
+		APIC_TDCR = 0x3E0,    // Divide Configuration (for Timer)
+	};
+
+	enum IOAPICRegisters
+	{
+		GetIOAPICVersion = 0x1
+	};
+
+	enum IOAPICFlags
+	{
+		ActiveHighLow = 2,
+		EdgeLevel = 8
+	};
+
+	enum APICDeliveryMode
+	{
+		Fixed = 0b000,
+		LowestPriority = 0b001, /* Reserved */
+		SMI = 0b010,
+		APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
+		NMI = 0b100,
+		INIT = 0b101,
+		Startup = 0b110,
+		ExtINT = 0b111 /* Reserved */
+	};
+
+	enum APICDestinationMode
+	{
+		Physical = 0b0,
+		Logical = 0b1
+	};
+
+	enum APICDeliveryStatus
+	{
+		Idle = 0b0,
+		SendPending = 0b1
+	};
+
+	enum APICLevel
+	{
+		DeAssert = 0b0,
+		Assert = 0b1
+	};
+
+	enum APICTriggerMode
+	{
+		Edge = 0b0,
+		Level = 0b1
+	};
+
+	enum APICDestinationShorthand
+	{
+		NoShorthand = 0b00,
+		Self = 0b01,
+		AllIncludingSelf = 0b10,
+		AllExcludingSelf = 0b11
+	};
+
+	enum LVTTimerDivide
+	{
+		DivideBy2 = 0b000,
+		DivideBy4 = 0b001,
+		DivideBy8 = 0b010,
+		DivideBy16 = 0b011,
+		DivideBy32 = 0b100,
+		DivideBy64 = 0b101,
+		DivideBy128 = 0b110,
+		DivideBy1 = 0b111
+	};
+
+	enum LVTTimerMask
+	{
+		Unmasked = 0b0,
+		Masked = 0b1
+	};
+
+	enum LVTTimerMode
+	{
+		OneShot = 0b00,
+		Periodic = 0b01,
+		TSCDeadline = 0b10
+	};
+
+	typedef union
+	{
+		struct
+		{
+			/** @brief Interrupt Vector */
+			uint64_t Vector : 8;
+			/** @brief Reserved */
+			uint64_t Reserved0 : 4;
+			/**
+			 * @brief Delivery Status
+			 *
+			 * 0: Idle
+			 * 1: Send Pending
+			 */
+			uint64_t DeliveryStatus : 1;
+			/** @brief Reserved */
+			uint64_t Reserved1 : 3;
+			/**
+			 * @brief Mask
+			 *
+			 * 0: Not masked
+			 * 1: Masked
+			 */
+			uint64_t Mask : 1;
+			/** @brief Timer Mode
+			 *
+			 * 0: One-shot
+			 * 1: Periodic
+			 * 2: TSC-Deadline
+			 */
+			uint64_t TimerMode : 1;
+			/** @brief Reserved */
+			uint64_t Reserved2 : 14;
+		};
+		uint64_t raw;
+	} __packed LVTTimer;
+
+	typedef union
+	{
+		struct
+		{
+			/** @brief Spurious Vector */
+			uint64_t Vector : 8;
+			/** @brief Enable or disable APIC software */
+			uint64_t Software : 1;
+			/** @brief Focus Processor Checking */
+			uint64_t FocusProcessorChecking : 1;
+			/** @brief Reserved */
+			uint64_t Reserved : 2;
+			/** @brief Disable EOI Broadcast */
+			uint64_t DisableEOIBroadcast : 1;
+			/** @brief Reserved */
+			uint64_t Reserved1 : 19;
+		};
+		uint64_t raw;
+	} __packed Spurious;
+
+	typedef union
+	{
+		struct
+		{
+			/** @brief Interrupt Vector */
+			uint64_t Vector : 8;
+			/** @brief Delivery Mode */
+			uint64_t DeliveryMode : 3;
+			/** @brief Destination Mode
+			 *
+			 * 0: Physical
+			 * 1: Logical
+			 */
+			uint64_t DestinationMode : 1;
+			/** @brief Delivery Status
+			 *
+			 * @note Reserved when in x2APIC mode
+			 */
+			uint64_t DeliveryStatus : 1;
+			/** @brief Reserved */
+			uint64_t Reserved0 : 1;
+			/** @brief Level
+			 *
+			 * 0: Deassert
+			 * 1: Assert
+			 */
+			uint64_t Level : 1;
+			/** @brief Trigger Mode
+			 *
+			 * 0: Edge
+			 * 1: Level
+			 */
+			uint64_t TriggerMode : 1;
+			/** @brief Reserved */
+			uint64_t Reserved1 : 2;
+			/** @brief Destination Shorthand
+			 *
+			 * 0: No shorthand
+			 * 1: Self
+			 * 2: All including self
+			 * 3: All excluding self
+			 */
+			uint64_t DestinationShorthand : 2;
+			/** @brief Reserved */
+			uint64_t Reserved2 : 12;
+		};
+		uint64_t raw;
+	} __packed InterruptCommandRegisterLow;
+
+	typedef union
+	{
+		struct
+		{
+			/** @brief Reserved */
+			uint64_t Reserved0 : 24;
+			/** @brief Destination */
+			uint64_t Destination : 8;
+		};
+		uint64_t raw;
+	} __packed InterruptCommandRegisterHigh;
+
+	typedef union
+	{
+		struct
+		{
+			/** @brief Interrupt Vector */
+			uint64_t Vector : 8;
+			/** @brief Delivery Mode */
+			uint64_t DeliveryMode : 3;
+			/** @brief Destination Mode
+			 *
+			 * 0: Physical
+			 * 1: Logical
+			 */
+			uint64_t DestinationMode : 1;
+			/** @brief Delivery Status */
+			uint64_t DeliveryStatus : 1;
+			/** @brief Interrupt Input Pin Polarity
+			 *
+			 * 0: Active High
+			 * 1: Active Low
+			 */
+			uint64_t Polarity : 1;
+			/** @brief Remote IRR */
+			uint64_t RemoteIRR : 1;
+			/** @brief Trigger Mode
+			 *
+			 * 0: Edge
+			 * 1: Level
+			 */
+			uint64_t TriggerMode : 1;
+			/** @brief Mask */
+			uint64_t Mask : 1;
+			/** @brief Reserved */
+			uint64_t Reserved0 : 15;
+			/** @brief Reserved */
+			uint64_t Reserved1 : 24;
+			/** @brief Destination */
+			uint64_t DestinationID : 8;
+		};
+		struct
+		{
+			uint64_t Low;
+			uint64_t High;
+		} split;
+		uint64_t raw;
+	} __packed IOAPICRedirectEntry;
+
+	typedef union
+	{
+		struct
+		{
+			uint64_t Version : 8;
+			uint64_t Reserved : 8;
+			uint64_t MaximumRedirectionEntry : 8;
+			uint64_t Reserved2 : 8;
+		};
+		uint64_t raw;
+	} __packed IOAPICVersion;
+
+	class APIC
+	{
+	private:
+		bool x2APICSupported = false;
+		uint64_t APICBaseAddress = 0;
+
+	public:
+		decltype(x2APICSupported) &x2APIC = x2APICSupported;
+
+		uint32_t Read(uint32_t Register);
+		void Write(uint32_t Register, uint32_t Value);
+		void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
+		uint32_t IORead(uint64_t Base, uint32_t Register);
+		void EOI();
+		void RedirectIRQs(int CPU = 0);
+		void WaitForIPI();
+		void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
+		void SendInitIPI(uint8_t CPU);
+		void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
+		uint32_t IOGetMaxRedirect(uint32_t APICID);
+		void RawRedirectIRQ(uint16_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
+		void RedirectIRQ(int CPU, uint16_t IRQ, int Status);
+		APIC(int Core);
+		~APIC();
+	};
+
+	class Timer : public Interrupts::Handler
+	{
+	private:
+		APIC *lapic;
+		uint64_t Ticks = 0;
+		void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
+
+	public:
+		uint64_t GetTicks() { return Ticks; }
+		void OneShot(uint32_t Vector, uint64_t Miliseconds);
+		Timer(APIC *apic);
+		~Timer();
+	};
+}
+
+#endif // !__FENNIX_KERNEL_APIC_H__

arch/i386/cpu/gdt.cpp

@@ -0,0 +1,262 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include "gdt.hpp"
+
+#include <memory.hpp>
+#include <smp.hpp>
+#include <cpu.hpp>
+#include <debug.h>
+
+namespace GlobalDescriptorTable
+{
+	static GlobalDescriptorTableEntries GDTEntriesTemplate = {
+		.Null =
+			{
+				.Limit0 = 0x0,
+				.BaseLow = 0x0,
+				.BaseMiddle = 0x0,
+				.Access = {.Raw = 0x0},
+				// .Limit1 = 0x0,
+				.Flags = {.Raw = 0x0},
+				.BaseHigh = 0x0,
+			},
+
+		.Code =
+			{
+				.Limit0 = 0xFFFF,
+				.BaseLow = 0x0,
+				.BaseMiddle = 0x0,
+				.Access = {
+					.A = 0,
+					.RW = 1,
+					.DC = 0,
+					.E = 1,
+					.S = 1,
+					.DPL = 0,
+					.P = 1,
+				},
+				// .Limit1 = 0xF,
+				.Flags = {
+					.Reserved = 0xF, /* Workaround for Limit1 */
+
+					.AVL = 0,
+					.L = 0,
+					.DB = 1,
+					.G = 1,
+				},
+				.BaseHigh = 0x0,
+			},
+
+		.Data = {
+			.Limit0 = 0xFFFF,
+			.BaseLow = 0x0,
+			.BaseMiddle = 0x0,
+			.Access = {
+				.A = 0,
+				.RW = 1,
+				.DC = 0,
+				.E = 0,
+				.S = 1,
+				.DPL = 0,
+				.P = 1,
+			},
+			// .Limit1 = 0xF,
+			.Flags = {
+				.Reserved = 0xF, /* Workaround for Limit1 */
+
+				.AVL = 0,
+				.L = 0,
+				.DB = 1,
+				.G = 1,
+			},
+			.BaseHigh = 0x0,
+		},
+
+		.UserData = {
+			.Limit0 = 0xFFFF,
+			.BaseLow = 0x0,
+			.BaseMiddle = 0x0,
+			.Access = {
+				.A = 0,
+				.RW = 1,
+				.DC = 0,
+				.E = 0,
+				.S = 1,
+				.DPL = 3,
+				.P = 1,
+			},
+			// .Limit1 = 0xF,
+			.Flags = {
+				.Reserved = 0xF, /* Workaround for Limit1 */
+
+				.AVL = 0,
+				.L = 0,
+				.DB = 1,
+				.G = 1,
+			},
+			.BaseHigh = 0x0,
+		},
+
+		.UserCode = {
+			.Limit0 = 0xFFFF,
+			.BaseLow = 0x0,
+			.BaseMiddle = 0x0,
+			.Access = {
+				.A = 0,
+				.RW = 1,
+				.DC = 0,
+				.E = 1,
+				.S = 1,
+				.DPL = 3,
+				.P = 1,
+			},
+			// .Limit1 = 0xF,
+			.Flags = {
+				.Reserved = 0xF, /* Workaround for Limit1 */
+
+				.AVL = 0,
+				.L = 0,
+				.DB = 1,
+				.G = 1,
+			},
+			.BaseHigh = 0x0,
+		},
+
+		.TaskStateSegment = {},
+	};
+
+	GlobalDescriptorTableEntries GDTEntries[MAX_CPU] __aligned(16);
+	GlobalDescriptorTableDescriptor gdt[MAX_CPU] __aligned(16);
+
+	TaskStateSegment tss[MAX_CPU] = {
+		0,
+		{0, 0, 0},
+		0,
+		{0, 0, 0, 0, 0, 0, 0},
+		0,
+		0,
+		0,
+	};
+
+	void *CPUStackPointer[MAX_CPU];
+
+	SafeFunction void Init(int Core)
+	{
+		memcpy(&GDTEntries[Core], &GDTEntriesTemplate, sizeof(GlobalDescriptorTableEntries));
+		gdt[Core] = {.Length = sizeof(GlobalDescriptorTableEntries) - 1, .Entries = &GDTEntries[Core]};
+
+		debug("GDT: %#lx", &gdt[Core]);
+		debug("GDT KERNEL: CODE %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
+			  GDT_KERNEL_CODE,
+			  GDTEntries[Core].Code.Limit0,
+			  GDTEntries[Core].Code.BaseLow,
+			  GDTEntries[Core].Code.BaseMiddle,
+			  GDTEntries[Core].Code.Access.Raw,
+			  GDTEntries[Core].Code.Flags.Reserved,
+			  GDTEntries[Core].Code.Flags.Raw & ~0xF,
+			  GDTEntries[Core].Code.BaseHigh);
+
+		debug("GDT KERNEL: DATA %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
+			  GDT_KERNEL_DATA,
+			  GDTEntries[Core].Data.Limit0,
+			  GDTEntries[Core].Data.BaseLow,
+			  GDTEntries[Core].Data.BaseMiddle,
+			  GDTEntries[Core].Data.Access.Raw,
+			  GDTEntries[Core].Data.Flags.Reserved,
+			  GDTEntries[Core].Data.Flags.Raw & ~0xF,
+			  GDTEntries[Core].Data.BaseHigh);
+
+		debug("GDT USER: CODE %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
+			  GDT_USER_CODE,
+			  GDTEntries[Core].UserCode.Limit0,
+			  GDTEntries[Core].UserCode.BaseLow,
+			  GDTEntries[Core].UserCode.BaseMiddle,
+			  GDTEntries[Core].UserCode.Access.Raw,
+			  GDTEntries[Core].UserCode.Flags.Reserved,
+			  GDTEntries[Core].UserCode.Flags.Raw & ~0xF,
+			  GDTEntries[Core].UserCode.BaseHigh);
+
+		debug("GDT USER: DATA %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
+			  GDT_USER_DATA,
+			  GDTEntries[Core].UserData.Limit0,
+			  GDTEntries[Core].UserData.BaseLow,
+			  GDTEntries[Core].UserData.BaseMiddle,
+			  GDTEntries[Core].UserData.Access.Raw,
+			  GDTEntries[Core].UserData.Flags.Reserved,
+			  GDTEntries[Core].UserData.Flags.Raw & ~0xF,
+			  GDTEntries[Core].UserData.BaseHigh);
+
+		CPU::x32::lgdt(&gdt[Core]);
+
+		asmv("mov %%esp, %%eax\n"
+			 "push $16\n"
+			 "push %%eax\n"
+			 "pushf\n"
+			 "push $8\n"
+			 "push $1f\n"
+			 "iret\n"
+			 "1:\n"
+			 "movw $16, %%ax\n"
+			 "movw %%ax, %%ds\n"
+			 "movw %%ax, %%es\n" ::
+				 : "memory", "eax");
+
+		CPUStackPointer[Core] = KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE + 1));
+		memset(CPUStackPointer[Core], 0, STACK_SIZE);
+		debug("CPU %d Stack Pointer: %#lx-%#lx (%d pages)", Core,
+			  CPUStackPointer[Core], (uintptr_t)CPUStackPointer[Core] + STACK_SIZE,
+			  TO_PAGES(STACK_SIZE + 1));
+
+		uintptr_t Base = (uintptr_t)&tss[Core];
+		size_t Limit = Base + sizeof(TaskStateSegment);
+		gdt[Core].Entries->TaskStateSegment.Limit = Limit & 0xFFFF;
+		gdt[Core].Entries->TaskStateSegment.BaseLow = Base & 0xFFFF;
+		gdt[Core].Entries->TaskStateSegment.BaseMiddle = uint8_t((Base >> 16) & 0xFF);
+		gdt[Core].Entries->TaskStateSegment.BaseHigh = uint8_t((Base >> 24) & 0xFF);
+
+#pragma GCC diagnostic ignored "-Wshift-count-overflow"
+		gdt[Core].Entries->TaskStateSegment.BaseUpper = s_cst(uint32_t, (Base >> 32) & 0xFFFFFFFF);
+
+		gdt[Core].Entries->TaskStateSegment.Access = {.A = 1, .RW = 0, .DC = 0, .E = 1, .S = 0, .DPL = 0, .P = 1};
+		gdt[Core].Entries->TaskStateSegment.Granularity = (0 << 4) | ((Limit >> 16) & 0xF);
+
+		tss[Core].IOMapBaseAddressOffset = sizeof(TaskStateSegment);
+		tss[Core].StackPointer[0] = (uint32_t)CPUStackPointer[Core] + STACK_SIZE;
+		tss[Core].StackPointer[1] = 0x0;
+		tss[Core].StackPointer[2] = 0x0;
+
+		for (size_t i = 0; i < sizeof(tss[Core].InterruptStackTable) / sizeof(tss[Core].InterruptStackTable[7]); i++)
+		{
+			void *NewStack = KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE + 1));
+
+			tss[Core].InterruptStackTable[i] = (uint32_t)NewStack + STACK_SIZE;
+			memset((void *)(tss[Core].InterruptStackTable[i] - STACK_SIZE), 0, STACK_SIZE);
+			debug("IST-%d: %#lx-%#lx", i, NewStack, (uintptr_t)NewStack + STACK_SIZE);
+		}
+
+		CPU::x32::ltr(GDT_TSS);
+		debug("Global Descriptor Table initialized");
+	}
+
+	SafeFunction void SetKernelStack(void *Stack)
+	{
+		stub;
+	}
+
+	void *GetKernelStack() { return (void *)nullptr; }
+}

arch/i386/cpu/gdt.hpp

@@ -0,0 +1,224 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#ifndef __FENNIX_KERNEL_GDT_H__
+#define __FENNIX_KERNEL_GDT_H__
+
+#include <types.h>
+
+namespace GlobalDescriptorTable
+{
+	struct TaskStateSegmentEntry
+	{
+		/* LOW */
+		uint16_t Limit;
+		uint16_t BaseLow;
+		uint8_t BaseMiddle;
+		union GlobalDescriptorTableAccess
+		{
+			struct
+			{
+				/** @brief Access bit.
+				 * @note The CPU sets this bit to 1 when the segment is accessed.
+				 */
+				uint8_t A : 1;
+
+				/** @brief Readable bit for code segments, writable bit for data segments.
+				 * @details For code segments, this bit must be 1 for the segment to be readable.
+				 * @details For data segments, this bit must be 1 for the segment to be writable.
+				 */
+				uint8_t RW : 1;
+
+				/** @brief Direction bit for data segments, conforming bit for code segments.
+				 * @details For data segments, this bit must be 1 for the segment to grow up (higher addresses).
+				 * @details For code segments, this bit must be 1 for code in the segment to be able to be executed from an equal or lower privilege level.
+				 */
+				uint8_t DC : 1;
+
+				/** @brief Executable bit.
+				 * @details This bit must be 1 for code-segment descriptors.
+				 * @details This bit must be 0 for data-segment and system descriptors.
+				 */
+				uint8_t E : 1;
+
+				/** @brief Descriptor type.
+				 * @details This bit must be 0 for system descriptors.
+				 * @details This bit must be 1 for code or data segment descriptor.
+				 */
+				uint8_t S : 1;
+
+				/** @brief Descriptor privilege level.
+				 * @details This field determines the privilege level of the segment.
+				 * @details 0 = kernel mode, 3 = user mode.
+				 */
+				uint8_t DPL : 2;
+
+				/** @brief Present bit.
+				 * @details This bit must be 1 for all valid descriptors.
+				 */
+				uint8_t P : 1;
+			} __packed;
+			uint8_t Raw : 8;
+		} Access;
+		uint8_t Granularity;
+		uint8_t BaseHigh;
+		/* HIGH */
+		uint32_t BaseUpper;
+		uint32_t Reserved;
+	} __packed;
+
+	struct TaskStateSegment
+	{
+		uint32_t Reserved0 __aligned(16);
+		uint64_t StackPointer[3];
+		uint64_t Reserved1;
+		uint64_t InterruptStackTable[7];
+		uint64_t Reserved2;
+		uint16_t Reserved3;
+		uint16_t IOMapBaseAddressOffset;
+	} __packed;
+
+	struct GlobalDescriptorTableEntry
+	{
+		/** @brief Limit 0:15 */
+		uint16_t Limit0 : 16;
+
+		/** @brief Low Base 0:15 */
+		uint16_t BaseLow : 16;
+
+		/** @brief Middle Base 16:23 */
+		uint8_t BaseMiddle : 8;
+
+		/** @brief Access */
+		union GlobalDescriptorTableAccess
+		{
+			struct
+			{
+				/** @brief Access bit.
+				 * @note The CPU sets this bit to 1 when the segment is accessed.
+				 */
+				uint8_t A : 1;
+
+				/** @brief Readable bit for code segments, writable bit for data segments.
+				 * @details For code segments, this bit must be 1 for the segment to be readable.
+				 * @details For data segments, this bit must be 1 for the segment to be writable.
+				 */
+				uint8_t RW : 1;
+
+				/** @brief Direction bit for data segments, conforming bit for code segments.
+				 * @details For data segments, this bit must be 1 for the segment to grow up (higher addresses).
+				 * @details For code segments, this bit must be 1 for code in the segment to be able to be executed from an equal or lower privilege level.
+				 */
+				uint8_t DC : 1;
+
+				/** @brief Executable bit.
+				 * @details This bit must be 1 for code-segment descriptors.
+				 * @details This bit must be 0 for data-segment and system descriptors.
+				 */
+				uint8_t E : 1;
+
+				/** @brief Descriptor type.
+				 * @details This bit must be 0 for system descriptors.
+				 * @details This bit must be 1 for code or data segment descriptor.
+				 */
+				uint8_t S : 1;
+
+				/** @brief Descriptor privilege level.
+				 * @details This field determines the privilege level of the segment.
+				 * @details 0 = kernel mode, 3 = user mode.
+				 */
+				uint8_t DPL : 2;
+
+				/** @brief Present bit.
+				 * @details This bit must be 1 for all valid descriptors.
+				 */
+				uint8_t P : 1;
+			} __packed;
+			uint8_t Raw : 8;
+		} Access;
+
+		// /** @brief Limit 16:19 */
+		// uint16_t Limit1 : 4;
+
+		/** @brief Flags */
+		union GlobalDescriptorTableFlags
+		{
+			struct
+			{
+				uint8_t Reserved : 4; /* FIXME: Without this, the kernel crashes. */
+				/** @brief Available bit.
+				 * @details This bit is available for use by system software.
+				 */
+				uint8_t AVL : 1;
+
+				/** @brief Long mode.
+				 * @details If the long mode bit is clear, the segment is in 32-bit protected mode.
+				 * @details If the long mode bit is set, the segment is in 64-bit long mode.
+				 */
+				uint8_t L : 1;
+
+				/** @brief Size flag.
+				 * @details If the size bit is clear, the segment is in 16-bit protected mode.
+				 * @details If the size bit is set, the segment is in 32-bit protected mode.
+				 */
+				uint8_t DB : 1;
+
+				/** @brief Granularity bit.
+				 * @details If the granularity bit is clear, the segment limit is in 1 B blocks.
+				 * @details If the granularity bit is set, the segment limit is in 4 KiB blocks.
+				 */
+				uint8_t G : 1;
+			} __packed;
+			uint8_t Raw : 8;
+		} Flags;
+
+		/** @brief High Base 24:31 */
+		uint8_t BaseHigh : 8;
+	} __packed;
+
+	struct GlobalDescriptorTableEntries
+	{
+		GlobalDescriptorTableEntry Null;
+		GlobalDescriptorTableEntry Code;
+		GlobalDescriptorTableEntry Data;
+		GlobalDescriptorTableEntry UserData;
+		GlobalDescriptorTableEntry UserCode;
+		TaskStateSegmentEntry TaskStateSegment;
+	} __packed;
+
+	struct GlobalDescriptorTableDescriptor
+	{
+		/** @brief GDT entries length */
+		uint16_t Length;
+		/** @brief GDT entries address */
+		GlobalDescriptorTableEntries *Entries;
+	} __packed;
+
+	extern void *CPUStackPointer[];
+	extern TaskStateSegment tss[];
+	void Init(int Core);
+	void SetKernelStack(void *Stack);
+	void *GetKernelStack();
+}
+
+#define GDT_KERNEL_CODE offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, Code)
+#define GDT_KERNEL_DATA offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, Data)
+#define GDT_USER_CODE (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, UserCode) | 3)
+#define GDT_USER_DATA (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, UserData) | 3)
+#define GDT_TSS (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, TaskStateSegment) | 3)
+
+#endif // !__FENNIX_KERNEL_GDT_H__

arch/i386/cpu/idt.cpp

@@ -0,0 +1,737 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include "idt.hpp"
+
+#include <memory.hpp>
+#include <cpu.hpp>
+#include <debug.h>
+#include <io.h>
+
+#include "gdt.hpp"
+#include "../../../kernel.h"
+
+/* conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘unsigned char:2’ may change value */
+#pragma GCC diagnostic ignored "-Wconversion"
+
+extern "C" void MainInterruptHandler(void *Data);
+extern "C" void ExceptionHandler(void *Data);
+
+namespace InterruptDescriptorTable
+{
+	__aligned(8) static IDTGateDescriptor Entries[0x100];
+
+	__aligned(8) IDTRegister IDTr = {
+		.Limit = sizeof(Entries) - 1,
+		.BaseAddress = Entries,
+	};
+
+	void SetEntry(uint8_t Index,
+				  void (*Base)(),
+				  GateType Gate,
+				  PrivilegeLevelType Ring,
+				  bool Present,
+				  uint16_t SegmentSelector)
+	{
+		switch (Gate)
+		{
+		case INTERRUPT_GATE_32BIT:
+		{
+			InterruptGate gate{
+				.TargetCodeSegmentOffsetLow = s_cst(uint16_t, ((uint32_t)Base & 0xFFFF)),
+				.TargetCodeSegmentSelector = SegmentSelector,
+				.Reserved0 = 0,
+				.Type = Gate,
+				.Zero = 0,
+				.DescriptorPrivilegeLevel = Ring,
+				.Present = Present,
+				.TargetCodeSegmentOffsetHigh = s_cst(uint16_t, ((uint32_t)Base >> 16)),
+			};
+			Entries[Index].Interrupt = gate;
+			break;
+		}
+		case TRAP_GATE_32BIT:
+		{
+			TrapGate gate{
+				.TargetCodeSegmentOffsetLow = s_cst(uint16_t, ((uint32_t)Base & 0xFFFF)),
+				.TargetCodeSegmentSelector = SegmentSelector,
+				.Reserved0 = 0,
+				.Type = Gate,
+				.Zero = 0,
+				.DescriptorPrivilegeLevel = Ring,
+				.Present = Present,
+				.TargetCodeSegmentOffsetHigh = s_cst(uint16_t, ((uint32_t)Base >> 16)),
+			};
+			Entries[Index].Trap = gate;
+			break;
+		}
+		case AVAILABLE_16BIT_TSS:
+		case LDT:
+		case BUSY_16BIT_TSS:
+		case CALL_GATE_16BIT:
+		case TASK_GATE:
+		case INTERRUPT_GATE_16BIT:
+		case TRAP_GATE_16BIT:
+		case AVAILABLE_32BIT_TSS:
+		case BUSY_32BIT_TSS:
+		case CALL_GATE_32BIT:
+		default:
+		{
+			assert(false);
+			break;
+		}
+		}
+	}
+
+	extern "C" __naked __used __no_stack_protector __aligned(16) void ExceptionHandlerStub()
+	{
+		asm("cld\n"
+			"cli\n"
+
+			"pusha\n"
+
+			"push %esp\n"
+			"call ExceptionHandler\n"
+			"pop %esp\n"
+
+			"popa\n"
+
+			"add $8, %esp\n"
+
+			"iret");
+	}
+
+	extern "C" __naked __used __no_stack_protector __aligned(16) void InterruptHandlerStub()
+	{
+		asm("cld\n"
+			"cli\n"
+
+			"pusha\n"
+
+			"push %esp\n"
+			"call MainInterruptHandler\n"
+			"pop %esp\n"
+
+			"popa\n"
+
+			"add $8, %esp\n"
+
+			"sti\n"
+			"iret");
+	}
+
+#pragma region Exceptions
+
+#define EXCEPTION_HANDLER(num)                                                             \
+	__naked __used __no_stack_protector __aligned(16) static void InterruptHandler_##num() \
+	{                                                                                      \
+		asm("push $0\npush $" #num "\n"                                                    \
+			"jmp ExceptionHandlerStub");                                                   \
+	}
+
+#define EXCEPTION_ERROR_HANDLER(num)                                                       \
+	__naked __used __no_stack_protector __aligned(16) static void InterruptHandler_##num() \
+	{                                                                                      \
+		asm("push $" #num "\n"                                                             \
+			"jmp ExceptionHandlerStub");                                                   \
+	}
+
+#define INTERRUPT_HANDLER(num)                                                      \
+	__naked __used __no_stack_protector __aligned(16) void InterruptHandler_##num() \
+	{                                                                               \
+		asm("push $0\npush $" #num "\n"                                             \
+			"jmp InterruptHandlerStub\n");                                          \
+	}
+
+	/* ISR */
+
+	EXCEPTION_HANDLER(0x0);
+	EXCEPTION_HANDLER(0x1);
+	EXCEPTION_HANDLER(0x2);
+	EXCEPTION_HANDLER(0x3);
+	EXCEPTION_HANDLER(0x4);
+	EXCEPTION_HANDLER(0x5);
+	EXCEPTION_HANDLER(0x6);
+	EXCEPTION_HANDLER(0x7);
+	EXCEPTION_ERROR_HANDLER(0x8);
+	EXCEPTION_HANDLER(0x9);
+	EXCEPTION_ERROR_HANDLER(0xa);
+	EXCEPTION_ERROR_HANDLER(0xb);
+	EXCEPTION_ERROR_HANDLER(0xc);
+	EXCEPTION_ERROR_HANDLER(0xd);
+	EXCEPTION_ERROR_HANDLER(0xe);
+	EXCEPTION_HANDLER(0xf);
+	EXCEPTION_ERROR_HANDLER(0x10);
+	EXCEPTION_HANDLER(0x11);
+	EXCEPTION_HANDLER(0x12);
+	EXCEPTION_HANDLER(0x13);
+	EXCEPTION_HANDLER(0x14);
+	EXCEPTION_HANDLER(0x15);
+	EXCEPTION_HANDLER(0x16);
+	EXCEPTION_HANDLER(0x17);
+	EXCEPTION_HANDLER(0x18);
+	EXCEPTION_HANDLER(0x19);
+	EXCEPTION_HANDLER(0x1a);
+	EXCEPTION_HANDLER(0x1b);
+	EXCEPTION_HANDLER(0x1c);
+	EXCEPTION_HANDLER(0x1d);
+	EXCEPTION_HANDLER(0x1e);
+	EXCEPTION_HANDLER(0x1f);
+
+	/* IRQ */
+
+	INTERRUPT_HANDLER(0x20)
+	INTERRUPT_HANDLER(0x21)
+	INTERRUPT_HANDLER(0x22)
+	INTERRUPT_HANDLER(0x23)
+	INTERRUPT_HANDLER(0x24)
+	INTERRUPT_HANDLER(0x25)
+	INTERRUPT_HANDLER(0x26)
+	INTERRUPT_HANDLER(0x27)
+	INTERRUPT_HANDLER(0x28)
+	INTERRUPT_HANDLER(0x29)
+	INTERRUPT_HANDLER(0x2a)
+	INTERRUPT_HANDLER(0x2b)
+	INTERRUPT_HANDLER(0x2c)
+	INTERRUPT_HANDLER(0x2d)
+	INTERRUPT_HANDLER(0x2e)
+	INTERRUPT_HANDLER(0x2f)
+
+	/* Reserved by OS */
+
+	INTERRUPT_HANDLER(0x30)
+	INTERRUPT_HANDLER(0x31)
+	INTERRUPT_HANDLER(0x32)
+	INTERRUPT_HANDLER(0x33)
+	INTERRUPT_HANDLER(0x34)
+	INTERRUPT_HANDLER(0x35)
+	INTERRUPT_HANDLER(0x36)
+	INTERRUPT_HANDLER(0x37)
+	INTERRUPT_HANDLER(0x38)
+	INTERRUPT_HANDLER(0x39)
+	INTERRUPT_HANDLER(0x3a)
+	INTERRUPT_HANDLER(0x3b)
+	INTERRUPT_HANDLER(0x3c)
+	INTERRUPT_HANDLER(0x3d)
+
+	/* Free */
+
+	INTERRUPT_HANDLER(0x3e)
+	INTERRUPT_HANDLER(0x3f)
+	INTERRUPT_HANDLER(0x40)
+	INTERRUPT_HANDLER(0x41)
+	INTERRUPT_HANDLER(0x42)
+	INTERRUPT_HANDLER(0x43)
+	INTERRUPT_HANDLER(0x44)
+	INTERRUPT_HANDLER(0x45)
+	INTERRUPT_HANDLER(0x46)
+	INTERRUPT_HANDLER(0x47)
+	INTERRUPT_HANDLER(0x48)
+	INTERRUPT_HANDLER(0x49)
+	INTERRUPT_HANDLER(0x4a)
+	INTERRUPT_HANDLER(0x4b)
+	INTERRUPT_HANDLER(0x4c)
+	INTERRUPT_HANDLER(0x4d)
+	INTERRUPT_HANDLER(0x4e)
+	INTERRUPT_HANDLER(0x4f)
+	INTERRUPT_HANDLER(0x50)
+	INTERRUPT_HANDLER(0x51)
+	INTERRUPT_HANDLER(0x52)
+	INTERRUPT_HANDLER(0x53)
+	INTERRUPT_HANDLER(0x54)
+	INTERRUPT_HANDLER(0x55)
+	INTERRUPT_HANDLER(0x56)
+	INTERRUPT_HANDLER(0x57)
+	INTERRUPT_HANDLER(0x58)
+	INTERRUPT_HANDLER(0x59)
+	INTERRUPT_HANDLER(0x5a)
+	INTERRUPT_HANDLER(0x5b)
+	INTERRUPT_HANDLER(0x5c)
+	INTERRUPT_HANDLER(0x5d)
+	INTERRUPT_HANDLER(0x5e)
+	INTERRUPT_HANDLER(0x5f)
+	INTERRUPT_HANDLER(0x60)
+	INTERRUPT_HANDLER(0x61)
+	INTERRUPT_HANDLER(0x62)
+	INTERRUPT_HANDLER(0x63)
+	INTERRUPT_HANDLER(0x64)
+	INTERRUPT_HANDLER(0x65)
+	INTERRUPT_HANDLER(0x66)
+	INTERRUPT_HANDLER(0x67)
+	INTERRUPT_HANDLER(0x68)
+	INTERRUPT_HANDLER(0x69)
+	INTERRUPT_HANDLER(0x6a)
+	INTERRUPT_HANDLER(0x6b)
+	INTERRUPT_HANDLER(0x6c)
+	INTERRUPT_HANDLER(0x6d)
+	INTERRUPT_HANDLER(0x6e)
+	INTERRUPT_HANDLER(0x6f)
+	INTERRUPT_HANDLER(0x70)
+	INTERRUPT_HANDLER(0x71)
+	INTERRUPT_HANDLER(0x72)
+	INTERRUPT_HANDLER(0x73)
+	INTERRUPT_HANDLER(0x74)
+	INTERRUPT_HANDLER(0x75)
+	INTERRUPT_HANDLER(0x76)
+	INTERRUPT_HANDLER(0x77)
+	INTERRUPT_HANDLER(0x78)
+	INTERRUPT_HANDLER(0x79)
+	INTERRUPT_HANDLER(0x7a)
+	INTERRUPT_HANDLER(0x7b)
+	INTERRUPT_HANDLER(0x7c)
+	INTERRUPT_HANDLER(0x7d)
+	INTERRUPT_HANDLER(0x7e)
+	INTERRUPT_HANDLER(0x7f)
+	INTERRUPT_HANDLER(0x80)
+	INTERRUPT_HANDLER(0x81)
+	INTERRUPT_HANDLER(0x82)
+	INTERRUPT_HANDLER(0x83)
+	INTERRUPT_HANDLER(0x84)
+	INTERRUPT_HANDLER(0x85)
+	INTERRUPT_HANDLER(0x86)
+	INTERRUPT_HANDLER(0x87)
+	INTERRUPT_HANDLER(0x88)
+	INTERRUPT_HANDLER(0x89)
+	INTERRUPT_HANDLER(0x8a)
+	INTERRUPT_HANDLER(0x8b)
+	INTERRUPT_HANDLER(0x8c)
+	INTERRUPT_HANDLER(0x8d)
+	INTERRUPT_HANDLER(0x8e)
+	INTERRUPT_HANDLER(0x8f)
+	INTERRUPT_HANDLER(0x90)
+	INTERRUPT_HANDLER(0x91)
+	INTERRUPT_HANDLER(0x92)
+	INTERRUPT_HANDLER(0x93)
+	INTERRUPT_HANDLER(0x94)
+	INTERRUPT_HANDLER(0x95)
+	INTERRUPT_HANDLER(0x96)
+	INTERRUPT_HANDLER(0x97)
+	INTERRUPT_HANDLER(0x98)
+	INTERRUPT_HANDLER(0x99)
+	INTERRUPT_HANDLER(0x9a)
+	INTERRUPT_HANDLER(0x9b)
+	INTERRUPT_HANDLER(0x9c)
+	INTERRUPT_HANDLER(0x9d)
+	INTERRUPT_HANDLER(0x9e)
+	INTERRUPT_HANDLER(0x9f)
+	INTERRUPT_HANDLER(0xa0)
+	INTERRUPT_HANDLER(0xa1)
+	INTERRUPT_HANDLER(0xa2)
+	INTERRUPT_HANDLER(0xa3)
+	INTERRUPT_HANDLER(0xa4)
+	INTERRUPT_HANDLER(0xa5)
+	INTERRUPT_HANDLER(0xa6)
+	INTERRUPT_HANDLER(0xa7)
+	INTERRUPT_HANDLER(0xa8)
+	INTERRUPT_HANDLER(0xa9)
+	INTERRUPT_HANDLER(0xaa)
+	INTERRUPT_HANDLER(0xab)
+	INTERRUPT_HANDLER(0xac)
+	INTERRUPT_HANDLER(0xad)
+	INTERRUPT_HANDLER(0xae)
+	INTERRUPT_HANDLER(0xaf)
+	INTERRUPT_HANDLER(0xb0)
+	INTERRUPT_HANDLER(0xb1)
+	INTERRUPT_HANDLER(0xb2)
+	INTERRUPT_HANDLER(0xb3)
+	INTERRUPT_HANDLER(0xb4)
+	INTERRUPT_HANDLER(0xb5)
+	INTERRUPT_HANDLER(0xb6)
+	INTERRUPT_HANDLER(0xb7)
+	INTERRUPT_HANDLER(0xb8)
+	INTERRUPT_HANDLER(0xb9)
+	INTERRUPT_HANDLER(0xba)
+	INTERRUPT_HANDLER(0xbb)
+	INTERRUPT_HANDLER(0xbc)
+	INTERRUPT_HANDLER(0xbd)
+	INTERRUPT_HANDLER(0xbe)
+	INTERRUPT_HANDLER(0xbf)
+	INTERRUPT_HANDLER(0xc0)
+	INTERRUPT_HANDLER(0xc1)
+	INTERRUPT_HANDLER(0xc2)
+	INTERRUPT_HANDLER(0xc3)
+	INTERRUPT_HANDLER(0xc4)
+	INTERRUPT_HANDLER(0xc5)
+	INTERRUPT_HANDLER(0xc6)
+	INTERRUPT_HANDLER(0xc7)
+	INTERRUPT_HANDLER(0xc8)
+	INTERRUPT_HANDLER(0xc9)
+	INTERRUPT_HANDLER(0xca)
+	INTERRUPT_HANDLER(0xcb)
+	INTERRUPT_HANDLER(0xcc)
+	INTERRUPT_HANDLER(0xcd)
+	INTERRUPT_HANDLER(0xce)
+	INTERRUPT_HANDLER(0xcf)
+	INTERRUPT_HANDLER(0xd0)
+	INTERRUPT_HANDLER(0xd1)
+	INTERRUPT_HANDLER(0xd2)
+	INTERRUPT_HANDLER(0xd3)
+	INTERRUPT_HANDLER(0xd4)
+	INTERRUPT_HANDLER(0xd5)
+	INTERRUPT_HANDLER(0xd6)
+	INTERRUPT_HANDLER(0xd7)
+	INTERRUPT_HANDLER(0xd8)
+	INTERRUPT_HANDLER(0xd9)
+	INTERRUPT_HANDLER(0xda)
+	INTERRUPT_HANDLER(0xdb)
+	INTERRUPT_HANDLER(0xdc)
+	INTERRUPT_HANDLER(0xdd)
+	INTERRUPT_HANDLER(0xde)
+	INTERRUPT_HANDLER(0xdf)
+	INTERRUPT_HANDLER(0xe0)
+	INTERRUPT_HANDLER(0xe1)
+	INTERRUPT_HANDLER(0xe2)
+	INTERRUPT_HANDLER(0xe3)
+	INTERRUPT_HANDLER(0xe4)
+	INTERRUPT_HANDLER(0xe5)
+	INTERRUPT_HANDLER(0xe6)
+	INTERRUPT_HANDLER(0xe7)
+	INTERRUPT_HANDLER(0xe8)
+	INTERRUPT_HANDLER(0xe9)
+	INTERRUPT_HANDLER(0xea)
+	INTERRUPT_HANDLER(0xeb)
+	INTERRUPT_HANDLER(0xec)
+	INTERRUPT_HANDLER(0xed)
+	INTERRUPT_HANDLER(0xee)
+	INTERRUPT_HANDLER(0xef)
+	INTERRUPT_HANDLER(0xf0)
+	INTERRUPT_HANDLER(0xf1)
+	INTERRUPT_HANDLER(0xf2)
+	INTERRUPT_HANDLER(0xf3)
+	INTERRUPT_HANDLER(0xf4)
+	INTERRUPT_HANDLER(0xf5)
+	INTERRUPT_HANDLER(0xf6)
+	INTERRUPT_HANDLER(0xf7)
+	INTERRUPT_HANDLER(0xf8)
+	INTERRUPT_HANDLER(0xf9)
+	INTERRUPT_HANDLER(0xfa)
+	INTERRUPT_HANDLER(0xfb)
+	INTERRUPT_HANDLER(0xfc)
+	INTERRUPT_HANDLER(0xfd)
+	INTERRUPT_HANDLER(0xfe)
+	INTERRUPT_HANDLER(0xff)
+
+#pragma endregion Exceptions
+
+	void Init(int Core)
+	{
+		if (Core == 0) /* Remap PIC using BSP */
+		{
+			// PIC
+			outb(0x20, 0x10 | 0x1);
+			outb(0x80, 0);
+			outb(0xA0, 0x10 | 0x10);
+			outb(0x80, 0);
+
+			outb(0x21, 0x20);
+			outb(0x80, 0);
+			outb(0xA1, 0x28);
+			outb(0x80, 0);
+
+			outb(0x21, 0x04);
+			outb(0x80, 0);
+			outb(0xA1, 0x02);
+			outb(0x80, 0);
+
+			outb(0x21, 1);
+			outb(0x80, 0);
+			outb(0xA1, 1);
+			outb(0x80, 0);
+
+			// Masking and disabling PIC
+			outb(0x21, 0xff);
+			outb(0x80, 0);
+			outb(0xA1, 0xff);
+		}
+
+		/* ISR */
+
+		bool EnableISRs = true;
+#ifdef DEBUG
+		EnableISRs = !DebuggerIsAttached;
+		if (!EnableISRs)
+			KPrint("\eFFA500The debugger is attached, disabling all ISRs.");
+#endif
+
+		SetEntry(0x0, InterruptHandler_0x0, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1, InterruptHandler_0x1, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x2, InterruptHandler_0x2, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x3, InterruptHandler_0x3, TRAP_GATE_32BIT, RING3, (!DebuggerIsAttached), GDT_KERNEL_CODE); /* Do not handle breakpoints if we are debugging the kernel. */
+		SetEntry(0x4, InterruptHandler_0x4, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x5, InterruptHandler_0x5, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x6, InterruptHandler_0x6, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x7, InterruptHandler_0x7, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x8, InterruptHandler_0x8, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x9, InterruptHandler_0x9, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0xa, InterruptHandler_0xa, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0xb, InterruptHandler_0xb, TRAP_GATE_32BIT, RING0, (!DebuggerIsAttached), GDT_KERNEL_CODE);
+		SetEntry(0xc, InterruptHandler_0xc, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0xd, InterruptHandler_0xd, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0xe, InterruptHandler_0xe, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0xf, InterruptHandler_0xf, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x10, InterruptHandler_0x10, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x11, InterruptHandler_0x11, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x12, InterruptHandler_0x12, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x13, InterruptHandler_0x13, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x14, InterruptHandler_0x14, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x15, InterruptHandler_0x15, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x16, InterruptHandler_0x16, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x17, InterruptHandler_0x17, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x18, InterruptHandler_0x18, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x19, InterruptHandler_0x19, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1a, InterruptHandler_0x1a, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1b, InterruptHandler_0x1b, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1c, InterruptHandler_0x1c, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1d, InterruptHandler_0x1d, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1e, InterruptHandler_0x1e, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+		SetEntry(0x1f, InterruptHandler_0x1f, TRAP_GATE_32BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
+
+		/* IRQ */
+
+		SetEntry(0x20, InterruptHandler_0x20, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x21, InterruptHandler_0x21, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x22, InterruptHandler_0x22, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x23, InterruptHandler_0x23, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x24, InterruptHandler_0x24, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x25, InterruptHandler_0x25, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x26, InterruptHandler_0x26, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x27, InterruptHandler_0x27, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x28, InterruptHandler_0x28, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x29, InterruptHandler_0x29, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2a, InterruptHandler_0x2a, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2b, InterruptHandler_0x2b, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2c, InterruptHandler_0x2c, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2d, InterruptHandler_0x2d, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2e, InterruptHandler_0x2e, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x2f, InterruptHandler_0x2f, INTERRUPT_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+
+		/* Reserved by OS */
+
+		SetEntry(0x30, InterruptHandler_0x30, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x31, InterruptHandler_0x31, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x32, InterruptHandler_0x32, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x33, InterruptHandler_0x33, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x34, InterruptHandler_0x34, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x35, InterruptHandler_0x35, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x36, InterruptHandler_0x36, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x37, InterruptHandler_0x37, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x38, InterruptHandler_0x38, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x39, InterruptHandler_0x39, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x3a, InterruptHandler_0x3a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x3b, InterruptHandler_0x3b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x3c, InterruptHandler_0x3c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x3d, InterruptHandler_0x3d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+
+		/* Free */
+
+		SetEntry(0x3e, InterruptHandler_0x3e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x3f, InterruptHandler_0x3f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x40, InterruptHandler_0x40, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x41, InterruptHandler_0x41, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x42, InterruptHandler_0x42, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x43, InterruptHandler_0x43, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x44, InterruptHandler_0x44, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x45, InterruptHandler_0x45, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x46, InterruptHandler_0x46, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x47, InterruptHandler_0x47, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x48, InterruptHandler_0x48, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x49, InterruptHandler_0x49, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4a, InterruptHandler_0x4a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4b, InterruptHandler_0x4b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4c, InterruptHandler_0x4c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4d, InterruptHandler_0x4d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4e, InterruptHandler_0x4e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x4f, InterruptHandler_0x4f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x50, InterruptHandler_0x50, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x51, InterruptHandler_0x51, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x52, InterruptHandler_0x52, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x53, InterruptHandler_0x53, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x54, InterruptHandler_0x54, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x55, InterruptHandler_0x55, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x56, InterruptHandler_0x56, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x57, InterruptHandler_0x57, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x58, InterruptHandler_0x58, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x59, InterruptHandler_0x59, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5a, InterruptHandler_0x5a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5b, InterruptHandler_0x5b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5c, InterruptHandler_0x5c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5d, InterruptHandler_0x5d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5e, InterruptHandler_0x5e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x5f, InterruptHandler_0x5f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x60, InterruptHandler_0x60, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x61, InterruptHandler_0x61, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x62, InterruptHandler_0x62, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x63, InterruptHandler_0x63, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x64, InterruptHandler_0x64, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x65, InterruptHandler_0x65, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x66, InterruptHandler_0x66, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x67, InterruptHandler_0x67, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x68, InterruptHandler_0x68, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x69, InterruptHandler_0x69, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6a, InterruptHandler_0x6a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6b, InterruptHandler_0x6b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6c, InterruptHandler_0x6c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6d, InterruptHandler_0x6d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6e, InterruptHandler_0x6e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x6f, InterruptHandler_0x6f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x70, InterruptHandler_0x70, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x71, InterruptHandler_0x71, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x72, InterruptHandler_0x72, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x73, InterruptHandler_0x73, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x74, InterruptHandler_0x74, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x75, InterruptHandler_0x75, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x76, InterruptHandler_0x76, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x77, InterruptHandler_0x77, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x78, InterruptHandler_0x78, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x79, InterruptHandler_0x79, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7a, InterruptHandler_0x7a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7b, InterruptHandler_0x7b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7c, InterruptHandler_0x7c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7d, InterruptHandler_0x7d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7e, InterruptHandler_0x7e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x7f, InterruptHandler_0x7f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x80, InterruptHandler_0x80, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x81, InterruptHandler_0x81, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x82, InterruptHandler_0x82, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x83, InterruptHandler_0x83, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x84, InterruptHandler_0x84, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x85, InterruptHandler_0x85, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x86, InterruptHandler_0x86, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x87, InterruptHandler_0x87, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x88, InterruptHandler_0x88, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x89, InterruptHandler_0x89, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8a, InterruptHandler_0x8a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8b, InterruptHandler_0x8b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8c, InterruptHandler_0x8c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8d, InterruptHandler_0x8d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8e, InterruptHandler_0x8e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x8f, InterruptHandler_0x8f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x90, InterruptHandler_0x90, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x91, InterruptHandler_0x91, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x92, InterruptHandler_0x92, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x93, InterruptHandler_0x93, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x94, InterruptHandler_0x94, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x95, InterruptHandler_0x95, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x96, InterruptHandler_0x96, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x97, InterruptHandler_0x97, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x98, InterruptHandler_0x98, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x99, InterruptHandler_0x99, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9a, InterruptHandler_0x9a, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9b, InterruptHandler_0x9b, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9c, InterruptHandler_0x9c, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9d, InterruptHandler_0x9d, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9e, InterruptHandler_0x9e, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0x9f, InterruptHandler_0x9f, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa0, InterruptHandler_0xa0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa1, InterruptHandler_0xa1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa2, InterruptHandler_0xa2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa3, InterruptHandler_0xa3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa4, InterruptHandler_0xa4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa5, InterruptHandler_0xa5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa6, InterruptHandler_0xa6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa7, InterruptHandler_0xa7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa8, InterruptHandler_0xa8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xa9, InterruptHandler_0xa9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xaa, InterruptHandler_0xaa, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xab, InterruptHandler_0xab, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xac, InterruptHandler_0xac, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xad, InterruptHandler_0xad, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xae, InterruptHandler_0xae, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xaf, InterruptHandler_0xaf, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb0, InterruptHandler_0xb0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb1, InterruptHandler_0xb1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb2, InterruptHandler_0xb2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb3, InterruptHandler_0xb3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb4, InterruptHandler_0xb4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb5, InterruptHandler_0xb5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb6, InterruptHandler_0xb6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb7, InterruptHandler_0xb7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb8, InterruptHandler_0xb8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xb9, InterruptHandler_0xb9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xba, InterruptHandler_0xba, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xbb, InterruptHandler_0xbb, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xbc, InterruptHandler_0xbc, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xbd, InterruptHandler_0xbd, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xbe, InterruptHandler_0xbe, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xbf, InterruptHandler_0xbf, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc0, InterruptHandler_0xc0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc1, InterruptHandler_0xc1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc2, InterruptHandler_0xc2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc3, InterruptHandler_0xc3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc4, InterruptHandler_0xc4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc5, InterruptHandler_0xc5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc6, InterruptHandler_0xc6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc7, InterruptHandler_0xc7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc8, InterruptHandler_0xc8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xc9, InterruptHandler_0xc9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xca, InterruptHandler_0xca, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xcb, InterruptHandler_0xcb, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xcc, InterruptHandler_0xcc, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xcd, InterruptHandler_0xcd, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xce, InterruptHandler_0xce, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xcf, InterruptHandler_0xcf, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd0, InterruptHandler_0xd0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd1, InterruptHandler_0xd1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd2, InterruptHandler_0xd2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd3, InterruptHandler_0xd3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd4, InterruptHandler_0xd4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd5, InterruptHandler_0xd5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd6, InterruptHandler_0xd6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd7, InterruptHandler_0xd7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd8, InterruptHandler_0xd8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xd9, InterruptHandler_0xd9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xda, InterruptHandler_0xda, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xdb, InterruptHandler_0xdb, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xdc, InterruptHandler_0xdc, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xdd, InterruptHandler_0xdd, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xde, InterruptHandler_0xde, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xdf, InterruptHandler_0xdf, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe0, InterruptHandler_0xe0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe1, InterruptHandler_0xe1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe2, InterruptHandler_0xe2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe3, InterruptHandler_0xe3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe4, InterruptHandler_0xe4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe5, InterruptHandler_0xe5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe6, InterruptHandler_0xe6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe7, InterruptHandler_0xe7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe8, InterruptHandler_0xe8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xe9, InterruptHandler_0xe9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xea, InterruptHandler_0xea, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xeb, InterruptHandler_0xeb, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xec, InterruptHandler_0xec, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xed, InterruptHandler_0xed, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xee, InterruptHandler_0xee, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xef, InterruptHandler_0xef, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf0, InterruptHandler_0xf0, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf1, InterruptHandler_0xf1, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf2, InterruptHandler_0xf2, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf3, InterruptHandler_0xf3, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf4, InterruptHandler_0xf4, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf5, InterruptHandler_0xf5, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf6, InterruptHandler_0xf6, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf7, InterruptHandler_0xf7, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf8, InterruptHandler_0xf8, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xf9, InterruptHandler_0xf9, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xfa, InterruptHandler_0xfa, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xfb, InterruptHandler_0xfb, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xfc, InterruptHandler_0xfc, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xfd, InterruptHandler_0xfd, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xfe, InterruptHandler_0xfe, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		SetEntry(0xff, InterruptHandler_0xff, TRAP_GATE_32BIT, RING0, true, GDT_KERNEL_CODE);
+		CPU::x32::lidt(&IDTr);
+	}
+}

arch/i386/cpu/idt.hpp

@@ -0,0 +1,144 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#ifndef __FENNIX_KERNEL_IDT_H__
+#define __FENNIX_KERNEL_IDT_H__
+
+#include <types.h>
+
+namespace InterruptDescriptorTable
+{
+	/**
+	 * Manual: AMD Architecture Programmer's Manual Volume 2: System Programming
+	 * Subsection: 4.7.4 System Descriptors
+	 * Table: 4-5
+	 *
+	 * @note Reserved values are not listed in the table.
+	 */
+	enum GateType
+	{
+		AVAILABLE_16BIT_TSS = 0b0001,
+		LDT = 0b0010,
+		BUSY_16BIT_TSS = 0b0011,
+		CALL_GATE_16BIT = 0b0100,
+		TASK_GATE = 0b0101,
+		INTERRUPT_GATE_16BIT = 0b0110,
+		TRAP_GATE_16BIT = 0b0111,
+		AVAILABLE_32BIT_TSS = 0b1001,
+		BUSY_32BIT_TSS = 0b1011,
+		CALL_GATE_32BIT = 0b1100,
+		INTERRUPT_GATE_32BIT = 0b1110,
+		TRAP_GATE_32BIT = 0b1111,
+	};
+
+	enum PrivilegeLevelType
+	{
+		RING0 = 0b0,
+		RING1 = 0b1,
+		RING2 = 0b10,
+		RING3 = 0b11,
+	};
+
+	struct LDTDescriptor
+	{
+		/* +0 */
+		uint32_t SegmentLimitLow : 16;
+		uint32_t BaseAddressLow : 16;
+		/* +4 */
+		uint32_t BaseAddressMiddle : 8;
+		uint32_t Type : 4;
+		uint32_t Zero : 1;
+		uint32_t DescriptorPrivilegeLevel : 2;
+		uint32_t Present : 1;
+		uint32_t SegmentLimitHigh : 4;
+		uint32_t Available : 1;
+		uint32_t Zero1 : 2;
+		uint32_t Granularity : 1;
+		uint32_t BaseAddressHigh : 8;
+	} __packed;
+
+	typedef LDTDescriptor TSSDescriptor;
+
+	struct CallGate
+	{
+		/* +0 */
+		uint32_t TargetCodeSegmentOffsetLow : 16;
+		uint32_t TargetCodeSegmentSelector : 16;
+		/* +4 */
+		uint32_t ParameterCount : 4;
+		uint32_t Reserved0 : 3;
+		uint32_t Type : 4;
+		uint32_t Zero : 1;
+		uint32_t DescriptorPrivilegeLevel : 2;
+		uint32_t Present : 1;
+		uint32_t TargetCodeSegmentOffsetHigh : 16;
+	} __packed;
+
+	struct InterruptGate
+	{
+		/* +0 */
+		uint32_t TargetCodeSegmentOffsetLow : 16;
+		uint32_t TargetCodeSegmentSelector : 16;
+		/* +4 */
+		uint32_t Reserved0 : 8;
+		uint32_t Type : 4;
+		uint32_t Zero : 1;
+		uint32_t DescriptorPrivilegeLevel : 2;
+		uint32_t Present : 1;
+		uint32_t TargetCodeSegmentOffsetHigh : 16;
+	} __packed;
+
+	typedef InterruptGate TrapGate;
+
+	struct TaskGate
+	{
+		/* +0 */
+		uint32_t Reserved0 : 16;
+		uint32_t TSSSelector : 16;
+		/* +4 */
+		uint32_t Reserved1 : 8;
+		uint32_t Type : 4;
+		uint32_t Zero : 1;
+		uint32_t DescriptorPrivilegeLevel : 2;
+		uint32_t Present : 1;
+		uint32_t Reserved2 : 16;
+	} __packed;
+
+	union IDTGateDescriptor
+	{
+		InterruptGate Interrupt;
+		TrapGate Trap;
+		CallGate Call;
+	};
+
+	struct IDTRegister
+	{
+		uint16_t Limit;
+		IDTGateDescriptor *BaseAddress;
+	} __packed;
+
+	void SetEntry(uint8_t Index,
+				  void (*Base)(),
+				  GateType Gate,
+				  PrivilegeLevelType Ring,
+				  bool Present,
+				  uint16_t SegmentSelector);
+
+	void Init(int Core);
+}
+
+#endif // !__FENNIX_KERNEL_IDT_H__

arch/i386/cpu/smp.cpp

@@ -0,0 +1,93 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <smp.hpp>
+
+#include <memory.hpp>
+#include <acpi.hpp>
+#include <ints.hpp>
+#include <assert.h>
+#include <cpu.hpp>
+#include <atomic>
+
+#include "../../../kernel.h"
+#include "apic.hpp"
+
+enum SMPTrampolineAddress
+{
+	PAGE_TABLE = 0x500,
+	START_ADDR = 0x520,
+	STACK = 0x570,
+	GDT = 0x580,
+	IDT = 0x590,
+	CORE = 0x600,
+	TRAMPOLINE_START = 0x2000
+};
+
+std::atomic_bool CPUEnabled = false;
+
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+static __aligned(PAGE_SIZE) CPUData CPUs[MAX_CPU] = {0};
+
+SafeFunction CPUData *GetCPU(long id) { return &CPUs[id]; }
+
+SafeFunction CPUData *GetCurrentCPU()
+{
+	if (unlikely(!Interrupts::apic[0]))
+		return &CPUs[0]; /* No APIC means we are on the BSP. */
+
+	APIC::APIC *apic = (APIC::APIC *)Interrupts::apic[0];
+	int CoreID = 0;
+	if (CPUEnabled.load(std::memory_order_acquire) == true)
+	{
+		if (apic->x2APIC)
+			CoreID = int(CPU::x32::rdmsr(CPU::x32::MSR_X2APIC_APICID));
+		else
+			CoreID = apic->Read(APIC::APIC_ID) >> 24;
+	}
+
+	if (unlikely((&CPUs[CoreID])->IsActive != true))
+	{
+		error("CPU %d is not active!", CoreID);
+		assert((&CPUs[0])->IsActive == true); /* We can't continue without the BSP. */
+		return &CPUs[0];
+	}
+
+	assert((&CPUs[CoreID])->Checksum == CPU_DATA_CHECKSUM); /* This should never happen. */
+	return &CPUs[CoreID];
+}
+
+namespace SMP
+{
+	int CPUCores = 0;
+
+	void Initialize(void *_madt)
+	{
+		ACPI::MADT *madt = (ACPI::MADT *)_madt;
+
+		int Cores = madt->CPUCores + 1;
+
+		if (Config.Cores > madt->CPUCores + 1)
+			KPrint("More cores requested than available. Using %d cores", madt->CPUCores + 1);
+		else if (Config.Cores != 0)
+			Cores = Config.Cores;
+
+		CPUCores = Cores;
+
+		fixme("SMP::Initialize() is not implemented!");
+	}
+}

arch/i386/interrupts/8259PIC.cpp

@@ -0,0 +1,140 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include "pic.hpp"
+
+#include <io.h>
+
+namespace PIC
+{
+    PIC::PIC(uint8_t MasterCommandPort, uint8_t MasterDataPort, uint8_t SlaveCommandPort, uint8_t SlaveDataPort, uint8_t MasterOffset, uint8_t SlaveOffset)
+    {
+        this->MasterCommandPort = MasterCommandPort;
+        this->MasterDataPort = MasterDataPort;
+        this->SlaveCommandPort = SlaveCommandPort;
+        this->SlaveDataPort = SlaveDataPort;
+        this->MasterOffset = MasterOffset;
+        this->SlaveOffset = SlaveOffset;
+
+        MasterMask = 0xFF;
+        SlaveMask = 0xFF;
+
+        // ICW1
+        outb(MasterCommandPort, 0x11);
+        outb(SlaveCommandPort, 0x11);
+
+        // ICW2
+        outb(MasterDataPort, MasterOffset);
+        outb(SlaveDataPort, SlaveOffset);
+
+        // ICW3
+        outb(MasterDataPort, 0x04);
+        outb(SlaveDataPort, 0x02);
+
+        // ICW4
+        outb(MasterDataPort, 0x01);
+        outb(SlaveDataPort, 0x01);
+
+        // OCW1
+        outb(MasterDataPort, MasterMask);
+        outb(SlaveDataPort, SlaveMask);
+    }
+
+    PIC::~PIC()
+    {
+        outb(MasterDataPort, 0xFF);
+        outb(SlaveDataPort, 0xFF);
+    }
+
+    void PIC::Mask(uint8_t IRQ)
+    {
+        uint16_t Port;
+        uint8_t Value;
+
+        if (IRQ < 8)
+        {
+            Port = MasterDataPort;
+            Value = (uint8_t)(MasterMask & ~(1 << IRQ));
+            MasterMask = Value;
+        }
+        else
+        {
+            Port = SlaveDataPort;
+            Value = (uint8_t)(SlaveMask & ~(1 << (IRQ - 8)));
+            SlaveMask = Value;
+        }
+
+        outb(Port, Value);
+    }
+
+    void PIC::Unmask(uint8_t IRQ)
+    {
+        uint16_t Port;
+        uint8_t Value;
+
+        if (IRQ < 8)
+        {
+            Port = MasterDataPort;
+            Value = MasterMask | (1 << IRQ);
+            MasterMask = Value;
+        }
+        else
+        {
+            Port = SlaveDataPort;
+            Value = SlaveMask | (1 << (IRQ - 8));
+            SlaveMask = Value;
+        }
+
+        outb(Port, Value);
+    }
+
+    void PIC::SendEOI(uint8_t IRQ)
+    {
+        if (IRQ >= 8)
+            outb(SlaveCommandPort, 0x20);
+
+        outb(MasterCommandPort, 0x20);
+    }
+
+    PIT::PIT(uint16_t Port, uint16_t Frequency)
+    {
+        this->Port = Port;
+        this->Frequency = Frequency;
+    }
+
+    PIT::~PIT()
+    {
+    }
+
+    void PIT::PrepareSleep(uint32_t Milliseconds)
+    {
+        uint16_t Divisor = (uint16_t)(1193182 / Frequency);
+        uint8_t Low = (uint8_t)(Divisor & 0xFF);
+        uint8_t High = (uint8_t)((Divisor >> 8) & 0xFF);
+
+        outb(Port + 3, 0x36);
+        outb(Port + 0, Low);
+        outb(Port + 1, High);
+    }
+
+    void PIT::PerformSleep()
+    {
+        uint8_t Value = inb(Port + 0);
+        while (Value != 0)
+            Value = inb(Port + 0);
+    }
+}

arch/i386/interrupts/pic.hpp

@@ -0,0 +1,59 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#ifndef __FENNIX_KERNEL_8259PIC_H__
+#define __FENNIX_KERNEL_8259PIC_H__
+
+#include <types.h>
+
+namespace PIC
+{
+    class PIC
+    {
+    private:
+        uint8_t MasterCommandPort;
+        uint8_t MasterDataPort;
+        uint8_t SlaveCommandPort;
+        uint8_t SlaveDataPort;
+        uint8_t MasterOffset;
+        uint8_t SlaveOffset;
+        uint8_t MasterMask;
+        uint8_t SlaveMask;
+
+    public:
+        PIC(uint8_t MasterCommandPort, uint8_t MasterDataPort, uint8_t SlaveCommandPort, uint8_t SlaveDataPort, uint8_t MasterOffset, uint8_t SlaveOffset);
+        ~PIC();
+        void Mask(uint8_t IRQ);
+        void Unmask(uint8_t IRQ);
+        void SendEOI(uint8_t IRQ);
+    };
+
+    class PIT
+    {
+    private:
+        uint16_t Port;
+        uint16_t Frequency;
+
+    public:
+        PIT(uint16_t Port, uint16_t Frequency);
+        ~PIT();
+        void PrepareSleep(uint32_t Milliseconds);
+        void PerformSleep();
+    };
+}
+
+#endif // !__FENNIX_KERNEL_8259PIC_H__

arch/i386/linker.ld

@@ -0,0 +1,104 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+OUTPUT_FORMAT(elf32-i386)
+OUTPUT_ARCH(i386)
+
+ENTRY(_start)
+
+PF_R = 0x4;
+PF_W = 0x2;
+PF_X = 0x1;
+
+PHDRS
+{
+    bootstrap   PT_LOAD    FLAGS( PF_R | PF_W /*| PF_X*/ );
+    text        PT_LOAD    FLAGS( PF_R | PF_X );
+    data        PT_LOAD    FLAGS( PF_R | PF_W );
+    rodata      PT_LOAD    FLAGS( PF_R );
+    bss         PT_LOAD    FLAGS( PF_R | PF_W );
+}
+
+KERNEL_VMA = 0xC0000000;
+
+SECTIONS
+{
+    . = 0x100000;
+    _bootstrap_start = .;
+    .bootstrap ALIGN(CONSTANT(MAXPAGESIZE)) :
+    {
+        *(.multiboot)
+        *(.multiboot2)
+        *(.bootstrap .bootstrap.*)
+    } :bootstrap
+    _bootstrap_end = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    . += KERNEL_VMA;
+
+    _kernel_start = ALIGN(CONSTANT(MAXPAGESIZE));
+    _kernel_text_start = ALIGN(CONSTANT(MAXPAGESIZE));
+    .text ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.text) - KERNEL_VMA)
+    {
+        *(.text .text.*)
+    } :text
+    _kernel_text_end = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    _kernel_data_start = ALIGN(CONSTANT(MAXPAGESIZE));
+    .data ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.data) - KERNEL_VMA)
+    {
+        *(.data .data.*)
+    } :data
+    _kernel_data_end = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    _kernel_rodata_start = ALIGN(CONSTANT(MAXPAGESIZE));
+    .rodata ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.rodata) - KERNEL_VMA)
+    {
+        *(.rodata .rodata.*)
+    } :rodata
+
+    .init_array ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.init_array) - KERNEL_VMA)
+    {
+        PROVIDE_HIDDEN(__init_array_start = .);
+        KEEP(*(.init_array .ctors))
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        PROVIDE_HIDDEN (__init_array_end = .);
+    } :rodata
+
+    .fini_array ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.fini_array) - KERNEL_VMA)
+    {
+        PROVIDE_HIDDEN(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+        KEEP(*(.fini_array .dtors))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+    } :rodata
+    _kernel_rodata_end = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    _kernel_bss_start = ALIGN(CONSTANT(MAXPAGESIZE));
+    .bss ALIGN(CONSTANT(MAXPAGESIZE)) : AT(ADDR(.bss) - KERNEL_VMA)
+    {
+        *(COMMON)
+        *(.bss .bss.*)
+    } :bss
+    _kernel_bss_end = ALIGN(CONSTANT(MAXPAGESIZE));
+    _kernel_end = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    /DISCARD/ :
+    {
+        *(.comment*)
+        *(.note*)
+    }
+}

arch/i386/madt.cpp

@@ -0,0 +1,91 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include "acpi.hpp"
+
+#include <memory.hpp>
+#include <debug.h>
+
+#include "../../kernel.h"
+
+namespace ACPI
+{
+	MADT::MADT(ACPI::MADTHeader *madt)
+	{
+		trace("Initializing MADT");
+		CPUCores = 0;
+		LAPICAddress = (LAPIC *)(uintptr_t)madt->LocalControllerAddress;
+		for (uint8_t *ptr = (uint8_t *)(madt->Entries);
+			 (uintptr_t)(ptr) < (uintptr_t)(madt) + madt->Header.Length;
+			 ptr += *(ptr + 1))
+		{
+			switch (*(ptr))
+			{
+			case 0:
+			{
+				if (ptr[4] & 1)
+				{
+					lapic.push_back((LocalAPIC *)ptr);
+					KPrint("Local APIC \e8888FF%d\eCCCCCC (APIC \e8888FF%d\eCCCCCC) found.", lapic.back()->ACPIProcessorId, lapic.back()->APICId);
+					CPUCores++;
+				}
+				break;
+			}
+			case 1:
+			{
+				ioapic.push_back((MADTIOApic *)ptr);
+				KPrint("I/O APIC \e8888FF%d\eCCCCCC (Address \e8888FF%#lx\eCCCCCC) found.", ioapic.back()->APICID, ioapic.back()->Address);
+				Memory::Virtual(KernelPageTable).Map((void *)(uintptr_t)ioapic.back()->Address, (void *)(uintptr_t)ioapic.back()->Address, Memory::PTFlag::RW | Memory::PTFlag::PCD); // Make sure that the address is mapped.
+				break;
+			}
+			case 2:
+			{
+				iso.push_back((MADTIso *)ptr);
+				KPrint("ISO (IRQ:\e8888FF%#lx\eCCCCCC, BUS:\e8888FF%#lx\eCCCCCC, GSI:\e8888FF%#lx\eCCCCCC, %s\eCCCCCC/%s\eCCCCCC) found.",
+					   iso.back()->IRQSource, iso.back()->BuSSource, iso.back()->GSI,
+					   iso.back()->Flags & 0x00000004 ? "\e1770FFActive High" : "\e475EFFActive Low",
+					   iso.back()->Flags & 0x00000100 ? "\e00962DEdge Triggered" : "\e008F58Level Triggered");
+				break;
+			}
+			case 4:
+			{
+				nmi.push_back((MADTNmi *)ptr);
+				KPrint("NMI \e8888FF%#lx\eCCCCCC (lint:\e8888FF%#lx\eCCCCCC) found.", nmi.back()->processor, nmi.back()->lint);
+				break;
+			}
+			case 5:
+			{
+				LAPICAddress = (LAPIC *)ptr;
+				KPrint("APIC found at \e8888FF%#lx\eCCCCCC", LAPICAddress);
+				break;
+			}
+			default:
+			{
+				KPrint("Unknown MADT entry \e8888FF%#lx\eCCCCCC", *(ptr));
+				break;
+			}
+			}
+			Memory::Virtual(KernelPageTable).Map((void *)LAPICAddress, (void *)LAPICAddress, Memory::PTFlag::RW | Memory::PTFlag::PCD); // I should map more than one page?
+		}
+		CPUCores--; // We start at 0 (BSP) and end at 11 (APs), so we have 12 cores.
+		KPrint("Total CPU cores: %d", CPUCores + 1);
+	}
+
+	MADT::~MADT()
+	{
+	}
+}

arch/i386/memory/vmm.cpp

@@ -0,0 +1,226 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <memory.hpp>
+
+#include <convert.h>
+#include <debug.h>
+
+namespace Memory
+{
+    bool Virtual::Check(void *VirtualAddress, PTFlag Flag, MapType Type)
+    {
+        // 0x1000 aligned
+        uintptr_t Address = (uintptr_t)VirtualAddress;
+        Address &= 0xFFFFF000;
+
+        PageMapIndexer Index = PageMapIndexer(Address);
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        PageTableEntryPtr *PTE = nullptr;
+
+        if ((PDE->raw & Flag) > 0)
+        {
+            if (Type == MapType::FourMiB && PDE->PageSize)
+                return true;
+
+            PTE = (PageTableEntryPtr *)((uintptr_t)PDE->GetAddress() << 12);
+            if (PTE)
+            {
+                if ((PTE->Entries[Index.PTEIndex].Present))
+                    return true;
+            }
+        }
+        return false;
+    }
+
+    void *Virtual::GetPhysical(void *VirtualAddress)
+    {
+        // 0x1000 aligned
+        uintptr_t Address = (uintptr_t)VirtualAddress;
+        Address &= 0xFFFFF000;
+
+        PageMapIndexer Index = PageMapIndexer(Address);
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        PageTableEntryPtr *PTE = nullptr;
+
+        if (PDE->Present)
+        {
+            if (PDE->PageSize)
+                return (void *)((uintptr_t)PDE->GetAddress() << 12);
+
+            PTE = (PageTableEntryPtr *)((uintptr_t)PDE->GetAddress() << 12);
+            if (PTE)
+            {
+                if (PTE->Entries[Index.PTEIndex].Present)
+                    return (void *)((uintptr_t)PTE->Entries[Index.PTEIndex].GetAddress() << 12);
+            }
+        }
+        return nullptr;
+    }
+
+    Virtual::MapType Virtual::GetMapType(void *VirtualAddress)
+    {
+        // 0x1000 aligned
+        uintptr_t Address = (uintptr_t)VirtualAddress;
+        Address &= 0xFFFFF000;
+
+        PageMapIndexer Index = PageMapIndexer(Address);
+
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        PageTableEntryPtr *PTE = nullptr;
+
+        if (PDE->Present)
+        {
+            if (PDE->PageSize)
+                return MapType::FourMiB;
+
+            PTE = (PageTableEntryPtr *)((uintptr_t)PDE->GetAddress() << 12);
+            if (PTE)
+            {
+                if (PTE->Entries[Index.PTEIndex].Present)
+                    return MapType::FourKiB;
+            }
+        }
+        return MapType::NoMapType;
+    }
+
+    PageDirectoryEntry *Virtual::GetPDE(void *VirtualAddress, MapType Type)
+    {
+        uintptr_t Address = (uintptr_t)VirtualAddress;
+        Address &= 0xFFFFF000;
+
+        PageMapIndexer Index = PageMapIndexer(Address);
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        if (PDE->Present)
+            return PDE;
+        return nullptr;
+    }
+
+    PageTableEntry *Virtual::GetPTE(void *VirtualAddress, MapType Type)
+    {
+        uintptr_t Address = (uintptr_t)VirtualAddress;
+        Address &= 0xFFFFF000;
+
+        PageMapIndexer Index = PageMapIndexer(Address);
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        if (!PDE->Present)
+            return nullptr;
+
+        PageTableEntryPtr *PTEPtr = (PageTableEntryPtr *)(PDE->GetAddress() << 12);
+        PageTableEntry *PTE = &PTEPtr->Entries[Index.PTEIndex];
+        if (PTE->Present)
+            return PTE;
+        return nullptr;
+    }
+
+    void Virtual::Map(void *VirtualAddress, void *PhysicalAddress, uint64_t Flags, MapType Type)
+    {
+        SmartLock(this->MemoryLock);
+        if (unlikely(!this->Table))
+        {
+            error("No page table");
+            return;
+        }
+
+        Flags |= PTFlag::P;
+
+        PageMapIndexer Index = PageMapIndexer((uintptr_t)VirtualAddress);
+        // Clear any flags that are not 1 << 0 (Present) - 1 << 5 (Accessed) because rest are for page table entries only
+        uint64_t DirectoryFlags = Flags & 0x3F;
+
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        if (Type == MapType::FourMiB)
+        {
+            PDE->raw |= (uintptr_t)Flags;
+            PDE->PageSize = true;
+            PDE->SetAddress((uintptr_t)PhysicalAddress >> 12);
+            debug("Mapped 4MB page at %p to %p", VirtualAddress, PhysicalAddress);
+            return;
+        }
+
+        PageTableEntryPtr *PTEPtr = nullptr;
+        if (!PDE->Present)
+        {
+            PTEPtr = (PageTableEntryPtr *)KernelAllocator.RequestPages(TO_PAGES(sizeof(PageTableEntryPtr) + 1));
+            memset(PTEPtr, 0, sizeof(PageTableEntryPtr));
+            PDE->Present = true;
+            PDE->SetAddress((uintptr_t)PTEPtr >> 12);
+        }
+        else
+            PTEPtr = (PageTableEntryPtr *)(PDE->GetAddress() << 12);
+        PDE->raw |= (uintptr_t)DirectoryFlags;
+
+        PageTableEntry *PTE = &PTEPtr->Entries[Index.PTEIndex];
+        PTE->Present = true;
+        PTE->raw |= (uintptr_t)Flags;
+        PTE->SetAddress((uintptr_t)PhysicalAddress >> 12);
+        CPU::x32::invlpg(VirtualAddress);
+
+#ifdef DEBUG
+/* https://stackoverflow.com/a/3208376/9352057 */
+#define BYTE_TO_BINARY_PATTERN "%c%c%c%c%c%c%c%c"
+#define BYTE_TO_BINARY(byte)       \
+    (byte & 0x80 ? '1' : '0'),     \
+        (byte & 0x40 ? '1' : '0'), \
+        (byte & 0x20 ? '1' : '0'), \
+        (byte & 0x10 ? '1' : '0'), \
+        (byte & 0x08 ? '1' : '0'), \
+        (byte & 0x04 ? '1' : '0'), \
+        (byte & 0x02 ? '1' : '0'), \
+        (byte & 0x01 ? '1' : '0')
+
+        if (!this->Check(VirtualAddress, (PTFlag)Flags, Type)) // quick workaround just to see where it fails
+            warn("Failed to map v:%#lx p:%#lx with flags: " BYTE_TO_BINARY_PATTERN, VirtualAddress, PhysicalAddress, BYTE_TO_BINARY(Flags));
+#endif
+    }
+
+    void Virtual::Unmap(void *VirtualAddress, MapType Type)
+    {
+        SmartLock(this->MemoryLock);
+        if (!this->Table)
+        {
+            error("No page table");
+            return;
+        }
+
+        PageMapIndexer Index = PageMapIndexer((uintptr_t)VirtualAddress);
+        PageDirectoryEntry *PDE = &this->Table->Entries[Index.PDEIndex];
+        if (!PDE->Present)
+        {
+            warn("Page %#lx not present", PDE->GetAddress());
+            return;
+        }
+
+        if (Type == MapType::FourMiB && PDE->PageSize)
+        {
+            PDE->Present = false;
+            return;
+        }
+
+        PageTableEntryPtr *PTEPtr = (PageTableEntryPtr *)((uintptr_t)PDE->Address << 12);
+        PageTableEntry PTE = PTEPtr->Entries[Index.PTEIndex];
+        if (!PTE.Present)
+        {
+            warn("Page %#lx not present", PTE.GetAddress());
+            return;
+        }
+
+        PTE.Present = false;
+        PTEPtr->Entries[Index.PTEIndex] = PTE;
+        CPU::x32::invlpg(VirtualAddress);
+    }
+}

arch/i386/syscalls.cpp

@@ -0,0 +1,30 @@
+/*
+	This file is part of Fennix Kernel.
+
+	Fennix Kernel is free software: you can redistribute it and/or
+	modify it under the terms of the GNU General Public License as
+	published by the Free Software Foundation, either version 3 of
+	the License, or (at your option) any later version.
+
+	Fennix Kernel is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
+*/
+
+#include <syscalls.hpp>
+
+#include <cpu.hpp>
+
+#include "cpu/gdt.hpp"
+
+using namespace CPU::x32;
+
+extern "C" uint32_t SystemCallsHandler(SyscallsFrame *regs);
+
+void InitializeSystemCalls()
+{
+}