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https://github.com/Fennix-Project/Kernel.git
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Move drivers to kernel
This commit is contained in:
Alex
400
include/pci.hpp
400
include/pci.hpp
@ -20,221 +20,223 @@
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#include <types.h>
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#include <memory.hpp>
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#include <debug.h>
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#include <vector>
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namespace PCI
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{
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namespace Descriptors
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{
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enum PCIVendors
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{
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SymbiosLogic = 0x1000,
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RedHat = 0x1AF4,
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REDHat2 = 0x1B36,
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Realtek = 0x10EC,
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VirtualBox = 0x80EE,
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Ensoniq = 0x1274,
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QEMU = 0x1234,
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VMware = 0x15AD,
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IntelCorporation = 0x8086,
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AdvancedMicroDevices = 0x1022,
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NVIDIACorporation = 0x10DE
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};
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namespace Descriptors
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{
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enum PCIVendors
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{
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SymbiosLogic = 0x1000,
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RedHat = 0x1AF4,
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REDHat2 = 0x1B36,
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Realtek = 0x10EC,
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VirtualBox = 0x80EE,
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Ensoniq = 0x1274,
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QEMU = 0x1234,
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VMware = 0x15AD,
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IntelCorporation = 0x8086,
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AdvancedMicroDevices = 0x1022,
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NVIDIACorporation = 0x10DE
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};
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const char *const DeviceClasses[]{
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"Unclassified",
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"Mass Storage Controller",
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"Network Controller",
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"Display Controller",
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"Multimedia Controller",
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"Memory Controller",
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"Bridge Device",
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"Simple Communication Controller",
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"Base System Peripheral",
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"Input Device Controller",
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"Docking Station",
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"Processor",
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"Serial Bus Controller",
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"Wireless Controller",
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"Intelligent Controller",
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"Satellite Communication Controller",
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"Encryption Controller",
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"Signal Processing Controller",
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"Processing Accelerator",
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"Non Essential Instrumentation"};
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const char *const DeviceClasses[]{
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"Unclassified",
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"Mass Storage Controller",
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"Network Controller",
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"Display Controller",
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"Multimedia Controller",
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"Memory Controller",
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"Bridge Device",
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"Simple Communication Controller",
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"Base System Peripheral",
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"Input Device Controller",
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"Docking Station",
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"Processor",
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"Serial Bus Controller",
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"Wireless Controller",
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"Intelligent Controller",
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"Satellite Communication Controller",
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"Encryption Controller",
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"Signal Processing Controller",
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"Processing Accelerator",
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"Non Essential Instrumentation"};
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const char *MassStorageControllerSubclassName(uint8_t SubclassCode);
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const char *NetworkControllerSubclassName(uint8_t SubclassCode);
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const char *DisplayControllerSubclassName(uint8_t SubclassCode);
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const char *CommunicationControllerSubclassName(uint8_t SubclassCode);
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const char *BaseSystemPeripheralSubclassName(uint8_t SubclassCode);
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const char *SerialBusControllerSubclassName(uint8_t SubclassCode);
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const char *BridgeDeviceSubclassName(uint8_t SubclassCode);
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const char *WirelessControllerSubclassName(uint8_t SubclassCode);
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const char *GetVendorName(uint32_t VendorID);
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const char *GetDeviceName(uint32_t VendorID, uint32_t DeviceID);
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const char *GetSubclassName(uint8_t ClassCode, uint8_t SubclassCode);
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const char *GetProgIFName(uint8_t ClassCode, uint8_t SubclassCode, uint8_t ProgIF);
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}
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const char *MassStorageControllerSubclassName(uint8_t SubclassCode);
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const char *NetworkControllerSubclassName(uint8_t SubclassCode);
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const char *DisplayControllerSubclassName(uint8_t SubclassCode);
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const char *CommunicationControllerSubclassName(uint8_t SubclassCode);
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const char *BaseSystemPeripheralSubclassName(uint8_t SubclassCode);
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const char *SerialBusControllerSubclassName(uint8_t SubclassCode);
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const char *BridgeDeviceSubclassName(uint8_t SubclassCode);
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const char *WirelessControllerSubclassName(uint8_t SubclassCode);
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const char *GetVendorName(uint32_t VendorID);
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const char *GetDeviceName(uint32_t VendorID, uint32_t DeviceID);
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const char *GetSubclassName(uint8_t ClassCode, uint8_t SubclassCode);
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const char *GetProgIFName(uint8_t ClassCode, uint8_t SubclassCode, uint8_t ProgIF);
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}
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/* https://sites.uclouvain.be/SystInfo/usr/include/linux/pci_regs.h.html */
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enum PCICommands
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{
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/** @brief Enable response in I/O space */
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PCI_COMMAND_IO = 0x1,
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/** @brief Enable response in Memory space */
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PCI_COMMAND_MEMORY = 0x2,
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/** @brief Enable bus mastering */
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PCI_COMMAND_MASTER = 0x4,
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/** @brief Enable response to special cycles */
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PCI_COMMAND_SPECIAL = 0x8,
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/** @brief Use memory write and invalidate */
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PCI_COMMAND_INVALIDATE = 0x10,
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/** @brief Enable palette snooping */
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PCI_COMMAND_VGA_PALETTE = 0x20,
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/** @brief Enable parity checking */
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PCI_COMMAND_PARITY = 0x40,
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/** @brief Enable address/data stepping */
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PCI_COMMAND_WAIT = 0x80,
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/** @brief Enable SERR */
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PCI_COMMAND_SERR = 0x100,
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/** @brief Enable back-to-back writes */
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PCI_COMMAND_FAST_BACK = 0x200,
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/** @brief INTx Emulation Disable */
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PCI_COMMAND_INTX_DISABLE = 0x400
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};
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/* https://sites.uclouvain.be/SystInfo/usr/include/linux/pci_regs.h.html */
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enum PCICommands
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{
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/** @brief Enable response in I/O space */
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PCI_COMMAND_IO = 0x1,
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/** @brief Enable response in Memory space */
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PCI_COMMAND_MEMORY = 0x2,
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/** @brief Enable bus mastering */
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PCI_COMMAND_MASTER = 0x4,
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/** @brief Enable response to special cycles */
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PCI_COMMAND_SPECIAL = 0x8,
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/** @brief Use memory write and invalidate */
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PCI_COMMAND_INVALIDATE = 0x10,
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/** @brief Enable palette snooping */
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PCI_COMMAND_VGA_PALETTE = 0x20,
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/** @brief Enable parity checking */
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PCI_COMMAND_PARITY = 0x40,
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/** @brief Enable address/data stepping */
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PCI_COMMAND_WAIT = 0x80,
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/** @brief Enable SERR */
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PCI_COMMAND_SERR = 0x100,
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/** @brief Enable back-to-back writes */
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PCI_COMMAND_FAST_BACK = 0x200,
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/** @brief INTx Emulation Disable */
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PCI_COMMAND_INTX_DISABLE = 0x400
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};
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struct PCIDeviceHeader
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{
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uint16_t VendorID;
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uint16_t DeviceID;
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uint16_t Command;
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uint16_t Status;
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uint8_t RevisionID;
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uint8_t ProgIF;
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uint8_t Subclass;
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uint8_t Class;
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uint8_t CacheLineSize;
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uint8_t LatencyTimer;
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uint8_t HeaderType;
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uint8_t BIST;
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};
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struct PCIDeviceHeader
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{
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uint16_t VendorID;
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uint16_t DeviceID;
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uint16_t Command;
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uint16_t Status;
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uint8_t RevisionID;
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uint8_t ProgIF;
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uint8_t Subclass;
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uint8_t Class;
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uint8_t CacheLineSize;
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uint8_t LatencyTimer;
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uint8_t HeaderType;
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uint8_t BIST;
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};
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/**
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* @brief PCI Header Type 0
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*
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*/
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struct PCIHeader0
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint32_t BAR2;
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uint32_t BAR3;
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uint32_t BAR4;
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uint32_t BAR5;
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uint32_t CardbusCISPointer;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t ExpansionROMBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t Reserved2;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint8_t MinGrant;
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uint8_t MaxLatency;
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};
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/**
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* @brief PCI Header Type 0
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*
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*/
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struct PCIHeader0
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint32_t BAR2;
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uint32_t BAR3;
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uint32_t BAR4;
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uint32_t BAR5;
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uint32_t CardbusCISPointer;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t ExpansionROMBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t Reserved2;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint8_t MinGrant;
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uint8_t MaxLatency;
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};
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/**
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* @brief PCI Header Type 1 (PCI-to-PCI Bridge)
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*/
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struct PCIHeader1
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint8_t PrimaryBusNumber;
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uint8_t SecondaryBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t SecondaryLatencyTimer;
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uint8_t IOBase;
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uint8_t IOLimit;
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uint16_t SecondaryStatus;
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uint16_t MemoryBase;
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uint16_t MemoryLimit;
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uint16_t PrefetchableMemoryBase;
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uint16_t PrefetchableMemoryLimit;
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uint32_t PrefetchableMemoryBaseUpper32;
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uint32_t PrefetchableMemoryLimitUpper32;
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uint16_t IOBaseUpper16;
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uint16_t IOLimitUpper16;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t ExpansionROMBaseAddress;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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};
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/**
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* @brief PCI Header Type 1 (PCI-to-PCI Bridge)
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*/
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struct PCIHeader1
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint8_t PrimaryBusNumber;
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uint8_t SecondaryBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t SecondaryLatencyTimer;
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uint8_t IOBase;
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uint8_t IOLimit;
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uint16_t SecondaryStatus;
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uint16_t MemoryBase;
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uint16_t MemoryLimit;
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uint16_t PrefetchableMemoryBase;
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uint16_t PrefetchableMemoryLimit;
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uint32_t PrefetchableMemoryBaseUpper32;
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uint32_t PrefetchableMemoryLimitUpper32;
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uint16_t IOBaseUpper16;
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uint16_t IOLimitUpper16;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t ExpansionROMBaseAddress;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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};
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/**
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* @brief PCI Header Type 2 (PCI-to-CardBus Bridge)
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*/
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struct PCIHeader2
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{
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PCIDeviceHeader Header;
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uint32_t CardbusSocketRegistersBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t SecondaryStatus;
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uint8_t PCIbusNumber;
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uint8_t CardbusBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t CardbusLatencyTimer;
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uint32_t MemoryBase0;
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uint32_t MemoryLimit0;
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uint32_t MemoryBase1;
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uint32_t MemoryLimit1;
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uint32_t IOBase0;
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uint32_t IOLimit0;
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uint32_t IOBase1;
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uint32_t IOLimit1;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t LegacyBaseAddress;
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};
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/**
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* @brief PCI Header Type 2 (PCI-to-CardBus Bridge)
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*/
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struct PCIHeader2
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{
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PCIDeviceHeader Header;
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uint32_t CardbusSocketRegistersBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t SecondaryStatus;
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uint8_t PCIbusNumber;
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uint8_t CardbusBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t CardbusLatencyTimer;
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uint32_t MemoryBase0;
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uint32_t MemoryLimit0;
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uint32_t MemoryBase1;
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uint32_t MemoryLimit1;
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uint32_t IOBase0;
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uint32_t IOLimit0;
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uint32_t IOBase1;
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uint32_t IOLimit1;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t LegacyBaseAddress;
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};
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struct DeviceConfig
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{
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uintptr_t BaseAddress;
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uint16_t PCISegGroup;
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uint8_t StartBus;
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uint8_t EndBus;
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uint32_t Reserved;
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} __packed;
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struct DeviceConfig
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{
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uintptr_t BaseAddress;
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uint16_t PCISegGroup;
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uint8_t StartBus;
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uint8_t EndBus;
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uint32_t Reserved;
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} __packed;
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class PCI
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{
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private:
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std::vector<PCIDeviceHeader *> Devices;
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class PCI
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{
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private:
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std::vector<PCIDeviceHeader *> Devices;
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public:
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std::vector<PCIDeviceHeader *> &GetDevices() { return Devices; }
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void EnumerateFunction(uintptr_t DeviceAddress, uintptr_t Function);
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void EnumerateDevice(uintptr_t BusAddress, uintptr_t Device);
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void EnumerateBus(uintptr_t BaseAddress, uintptr_t Bus);
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std::vector<PCIDeviceHeader *> FindPCIDevice(uint8_t Class, uint8_t Subclass, uint8_t ProgIF);
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std::vector<PCIDeviceHeader *> FindPCIDevice(int VendorID, int DeviceID);
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public:
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std::vector<PCIDeviceHeader *> &GetDevices() { return Devices; }
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void MapPCIAddresses(PCIDeviceHeader *PCIDevice, Memory::PageTable *Table = nullptr);
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void EnumerateFunction(uintptr_t DeviceAddress, uintptr_t Function);
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void EnumerateDevice(uintptr_t BusAddress, uintptr_t Device);
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void EnumerateBus(uintptr_t BaseAddress, uintptr_t Bus);
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std::vector<PCIDeviceHeader *> FindPCIDevice(uint8_t Class, uint8_t Subclass, uint8_t ProgIF);
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std::vector<PCIDeviceHeader *> FindPCIDevice(int VendorID, int DeviceID);
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PCI();
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~PCI();
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};
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PCI();
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~PCI();
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};
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}
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#endif // !__FENNIX_KERNEL_PCI_H__
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