mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-07-11 07:19:20 +00:00
Implemented a kinda broken tty
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179
include/cpu.hpp
179
include/cpu.hpp
@ -8,127 +8,134 @@
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*/
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namespace CPU
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{
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/**
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* @brief Enum for CPU::Interrupts() function.
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*/
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enum InterruptsType
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{
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/**
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* @brief Check if interrupts are enabled.
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* @brief Enum for CPU::Interrupts() function.
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*/
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Check,
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enum InterruptsType
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{
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/**
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* @brief Check if interrupts are enabled.
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*/
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Check,
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/**
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* @brief Enable interrupts.
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*/
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Enable,
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/**
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* @brief Disable interrupts.
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*/
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Disable
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};
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/**
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* @brief Enable interrupts.
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* @brief Pause the CPU
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*/
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Enable,
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void Pause();
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/**
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* @brief Disable interrupts.
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* @brief Halt the CPU
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*/
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Disable
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};
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void Halt();
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/**
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* @brief Check if interrupts are enabled
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*
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* @return true If InterruptsType::Check and interrupts are enabled, or if other InterruptsType were executed successfully
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* @return false If InterruptsType::Check and interrupts are disabled, or if other InterruptsType failed
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*/
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bool Interrupts(InterruptsType Type = Check);
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/**
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* @brief Get/Set the CPU's page table
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*
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* @param PT The new page table, if empty, the current page table will be returned
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* @return void* The current page table
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*/
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void *PageTable(void *PT = nullptr);
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/**
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* @brief Pause the CPU
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*/
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void Pause();
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/**
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* @brief Halt the CPU
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*/
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void Halt();
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/**
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* @brief Check if interrupts are enabled
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*
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* @return true If InterruptsType::Check and interrupts are enabled, or if other InterruptsType were executed successfully
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* @return false If InterruptsType::Check and interrupts are disabled, or if other InterruptsType failed
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*/
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bool Interrupts(InterruptsType Type = Check);
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namespace MemBar
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{
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static inline void Barrier()
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namespace MemBar
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{
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static inline void Barrier()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("" ::
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: "memory");
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asmv("" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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}
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static inline void Fence()
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{
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static inline void Fence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("mfence" ::
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: "memory");
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asmv("mfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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}
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static inline void StoreFence()
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{
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static inline void StoreFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("sfence" ::
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: "memory");
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asmv("sfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishst" ::
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: "memory");
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asmv("dmb ishst" ::
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: "memory");
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#endif
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}
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}
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static inline void LoadFence()
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{
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static inline void LoadFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lfence" ::
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: "memory");
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asmv("lfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishld" ::
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: "memory");
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#endif
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}
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}
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namespace x86
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{
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lgdt (%0)"
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:
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: "r"(gdt));
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asmv("dmb ishld" ::
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: "memory");
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#endif
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}
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}
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static inline void lidt(void *idt)
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namespace x86
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{
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lidt (%0)"
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:
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: "r"(idt));
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asmv("lgdt (%0)"
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:
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: "r"(gdt));
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#endif
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}
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}
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static inline void ltr(uint16_t Segment)
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{
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static inline void lidt(void *idt)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("ltr %0"
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:
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: "r"(Segment));
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asmv("lidt (%0)"
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:
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: "r"(idt));
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#endif
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}
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}
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static inline void invlpg(void *Address)
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{
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static inline void ltr(uint16_t Segment)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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asmv("ltr %0"
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:
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: "r"(Segment));
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#endif
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}
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static inline void invlpg(void *Address)
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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#endif
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}
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}
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}
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}
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#endif // !__FENNIX_KERNEL_CPU_H__
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