From 76239ec4adb0fd03db1a42438041bd0676a18ae9 Mon Sep 17 00:00:00 2001 From: Alex Date: Thu, 6 Apr 2023 18:36:16 +0300 Subject: [PATCH] Add Get() function for every cpuid struct --- ...dvancedProgrammableInterruptController.cpp | 30 +- Core/CPU.cpp | 124 +- Core/Random.cpp | 84 +- Tasking/Task.cpp | 28 +- Tests/RandomNumberGenerator.cpp | 28 +- include/cpu.hpp | 8 +- include/cpu/x86/{x64 => }/cpuid_amd.hpp | 1068 +++++++++++------ include/cpu/x86/{x64 => }/cpuid_intel.hpp | 840 ++++++++----- include/cpu/x86/x32/cpuid_amd.hpp | 627 ---------- include/cpu/x86/x32/cpuid_intel.hpp | 965 --------------- 10 files changed, 1283 insertions(+), 2519 deletions(-) rename include/cpu/x86/{x64 => }/cpuid_amd.hpp (56%) rename include/cpu/x86/{x64 => }/cpuid_intel.hpp (55%) delete mode 100644 include/cpu/x86/x32/cpuid_amd.hpp delete mode 100644 include/cpu/x86/x32/cpuid_intel.hpp diff --git a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp index 6e5c7f3..29c3cc9 100644 --- a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp +++ b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp @@ -258,35 +258,19 @@ namespace APIC bool x2APICSupported = false; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); -#endif - if (cpuid1amd.ECX.x2APIC) + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + if (cpuid.ECX.x2APIC) { - // x2APICSupported = cpuid1amd.ECX.x2APIC; + // x2APICSupported = cpuid.ECX.x2APIC; fixme("x2APIC is supported"); } } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); -#endif - x2APICSupported = cpuid1intel.ECX.x2APIC; + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + x2APICSupported = cpuid.ECX.x2APIC; } if (x2APICSupported) diff --git a/Core/CPU.cpp b/Core/CPU.cpp index 5bede1e..6641771 100644 --- a/Core/CPU.cpp +++ b/Core/CPU.cpp @@ -204,36 +204,20 @@ namespace CPU if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); -#endif - if (cpuid1amd.EDX.PGE) + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + if (cpuid.EDX.PGE) PGESupport = true; - if (cpuid1amd.EDX.SSE) + if (cpuid.EDX.SSE) SSESupport = true; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); -#endif - if (cpuid1intel.EDX.PGE) + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + if (cpuid.EDX.PGE) PGESupport = true; - if (cpuid1intel.EDX.SSE) + if (cpuid.EDX.SSE) SSESupport = true; } @@ -376,36 +360,32 @@ namespace CPU if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif + CPU::x86::AMD::CPUID0x00000001 cpuid; asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) + : "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw) : "a"(0x1)); - if (cpuid1amd.ECX.SSE42) + if (cpuid.ECX.SSE42) SIMDType |= SIMD_SSE42; - else if (cpuid1amd.ECX.SSE41) + else if (cpuid.ECX.SSE41) SIMDType |= SIMD_SSE41; - else if (cpuid1amd.ECX.SSE3) + else if (cpuid.ECX.SSE3) SIMDType |= SIMD_SSE3; - else if (cpuid1amd.EDX.SSE2) + else if (cpuid.EDX.SSE2) SIMDType |= SIMD_SSE2; - else if (cpuid1amd.EDX.SSE) + else if (cpuid.EDX.SSE) SIMDType |= SIMD_SSE; #ifdef DEBUG - if (cpuid1amd.ECX.SSE42) + if (cpuid.ECX.SSE42) debug("SSE4.2 is supported."); - if (cpuid1amd.ECX.SSE41) + if (cpuid.ECX.SSE41) debug("SSE4.1 is supported."); - if (cpuid1amd.ECX.SSE3) + if (cpuid.ECX.SSE3) debug("SSE3 is supported."); - if (cpuid1amd.EDX.SSE2) + if (cpuid.EDX.SSE2) debug("SSE2 is supported."); - if (cpuid1amd.EDX.SSE) + if (cpuid.EDX.SSE) debug("SSE is supported."); #endif @@ -413,36 +393,32 @@ namespace CPU } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif + CPU::x86::Intel::CPUID0x00000001 cpuid; asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) + : "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw) : "a"(0x1)); - if (cpuid1intel.ECX.SSE4_2) + if (cpuid.ECX.SSE4_2) SIMDType |= SIMD_SSE42; - else if (cpuid1intel.ECX.SSE4_1) + else if (cpuid.ECX.SSE4_1) SIMDType |= SIMD_SSE41; - else if (cpuid1intel.ECX.SSE3) + else if (cpuid.ECX.SSE3) SIMDType |= SIMD_SSE3; - else if (cpuid1intel.EDX.SSE2) + else if (cpuid.EDX.SSE2) SIMDType |= SIMD_SSE2; - else if (cpuid1intel.EDX.SSE) + else if (cpuid.EDX.SSE) SIMDType |= SIMD_SSE; #ifdef DEBUG - if (cpuid1intel.ECX.SSE4_2) + if (cpuid.ECX.SSE4_2) debug("SSE4.2 is supported."); - if (cpuid1intel.ECX.SSE4_1) + if (cpuid.ECX.SSE4_1) debug("SSE4.1 is supported."); - if (cpuid1intel.ECX.SSE3) + if (cpuid.ECX.SSE3) debug("SSE3 is supported."); - if (cpuid1intel.EDX.SSE2) + if (cpuid.EDX.SSE2) debug("SSE2 is supported."); - if (cpuid1intel.EDX.SSE) + if (cpuid.EDX.SSE) debug("SSE is supported."); #endif return SIMDType; @@ -461,47 +437,39 @@ namespace CPU #if defined(a64) || defined(a32) if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif + CPU::x86::AMD::CPUID0x00000001 cpuid; asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) + : "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw) : "a"(0x1)); if (Type == SIMD_SSE42) - return cpuid1amd.ECX.SSE42; + return cpuid.ECX.SSE42; else if (Type == SIMD_SSE41) - return cpuid1amd.ECX.SSE41; + return cpuid.ECX.SSE41; else if (Type == SIMD_SSE3) - return cpuid1amd.ECX.SSE3; + return cpuid.ECX.SSE3; else if (Type == SIMD_SSE2) - return cpuid1amd.EDX.SSE2; + return cpuid.EDX.SSE2; else if (Type == SIMD_SSE) - return cpuid1amd.EDX.SSE; + return cpuid.EDX.SSE; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif + CPU::x86::Intel::CPUID0x00000001 cpuid; asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) + : "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw) : "a"(0x1)); if (Type == SIMD_SSE42) - return cpuid1intel.ECX.SSE4_2; + return cpuid.ECX.SSE4_2; else if (Type == SIMD_SSE41) - return cpuid1intel.ECX.SSE4_1; + return cpuid.ECX.SSE4_1; else if (Type == SIMD_SSE3) - return cpuid1intel.ECX.SSE3; + return cpuid.ECX.SSE3; else if (Type == SIMD_SSE2) - return cpuid1intel.EDX.SSE2; + return cpuid.EDX.SSE2; else if (Type == SIMD_SSE) - return cpuid1intel.EDX.SSE; + return cpuid.EDX.SSE; } #endif // a64 || a32 return false; diff --git a/Core/Random.cpp b/Core/Random.cpp index 414f033..b1aabcf 100644 --- a/Core/Random.cpp +++ b/Core/Random.cpp @@ -27,31 +27,15 @@ namespace Random int RDRANDFlag = 0; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1amd.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1intel.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0) @@ -76,31 +60,15 @@ namespace Random int RDRANDFlag = 0; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1amd.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1intel.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0) @@ -125,31 +93,15 @@ namespace Random int RDRANDFlag = 0; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1amd.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1intel.ECX.RDRAND; -#endif // a64 || a32 + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0) diff --git a/Tasking/Task.cpp b/Tasking/Task.cpp index 0c080af..7be4ca6 100644 --- a/Tasking/Task.cpp +++ b/Tasking/Task.cpp @@ -803,31 +803,15 @@ namespace Tasking bool MONITORSupported = false; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); - MONITORSupported = cpuid1amd.ECX.MONITOR; -#endif + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + MONITORSupported = cpuid.ECX.MONITOR; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); - MONITORSupported = cpuid1intel.ECX.MONITOR; -#endif + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + MONITORSupported = cpuid.ECX.MONITOR; } if (MONITORSupported) diff --git a/Tests/RandomNumberGenerator.cpp b/Tests/RandomNumberGenerator.cpp index e5800f8..10eb40f 100644 --- a/Tests/RandomNumberGenerator.cpp +++ b/Tests/RandomNumberGenerator.cpp @@ -26,31 +26,15 @@ __constructor void TestRandom() int RDRANDFlag = 0; if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0) { -#if defined(a64) - CPU::x64::AMD::CPUID0x00000001 cpuid1amd; -#elif defined(a32) - CPU::x32::AMD::CPUID0x00000001 cpuid1amd; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1amd.ECX.RDRAND; -#endif + CPU::x86::AMD::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0) { -#if defined(a64) - CPU::x64::Intel::CPUID0x00000001 cpuid1intel; -#elif defined(a32) - CPU::x32::Intel::CPUID0x00000001 cpuid1intel; -#endif -#if defined(a64) || defined(a32) - asmv("cpuid" - : "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw) - : "a"(0x1)); - RDRANDFlag = cpuid1intel.ECX.RDRAND; -#endif + CPU::x86::Intel::CPUID0x00000001 cpuid; + cpuid.Get(); + RDRANDFlag = cpuid.ECX.RDRAND; } if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0) diff --git a/include/cpu.hpp b/include/cpu.hpp index b2daaa1..4ce07dc 100644 --- a/include/cpu.hpp +++ b/include/cpu.hpp @@ -20,19 +20,17 @@ #include -#include -#include -#include +#include +#include #include #include -#include -#include #include #include #include #include #include #include +#include /** * @brief CPU related functions. diff --git a/include/cpu/x86/x64/cpuid_amd.hpp b/include/cpu/x86/cpuid_amd.hpp similarity index 56% rename from include/cpu/x86/x64/cpuid_amd.hpp rename to include/cpu/x86/cpuid_amd.hpp index 4357da2..9a66cef 100644 --- a/include/cpu/x86/x64/cpuid_amd.hpp +++ b/include/cpu/x86/cpuid_amd.hpp @@ -15,14 +15,14 @@ along with Fennix Kernel. If not, see . */ -#ifndef __FENNIX_KERNEL_CPU_x64_CPUID_AMD_H__ -#define __FENNIX_KERNEL_CPU_x64_CPUID_AMD_H__ +#ifndef __FENNIX_KERNEL_CPU_x86_CPUID_AMD_H__ +#define __FENNIX_KERNEL_CPU_x86_CPUID_AMD_H__ #include namespace CPU { - namespace x64 + namespace x86 { /** @brief EXPERIMENTAL IMPLEMENTATION */ namespace AMD @@ -30,12 +30,21 @@ namespace CPU /** @brief Basic CPU information */ struct CPUID0x00000000 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Largest Standard Function Number */ union { struct { - uint64_t LFuncStd : 32; + uint32_t LFuncStd : 32; }; uint64_t raw; } EAX; @@ -74,19 +83,28 @@ namespace CPU /** @brief Additional CPU information */ struct CPUID0x00000001 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Family, Model, Stepping Identifiers */ union { /* "This function is an identical copy of CPUID Fn8000_0001_EAX." */ struct { - uint64_t Stepping : 4; - uint64_t BaseModel : 4; - uint64_t BaseFamily : 4; - uint64_t Reserved0 : 4; - uint64_t ExtModel : 4; - uint64_t ExtFamily : 8; - uint64_t Reserved1 : 4; + uint32_t Stepping : 4; + uint32_t BaseModel : 4; + uint32_t BaseFamily : 4; + uint32_t Reserved0 : 4; + uint32_t ExtModel : 4; + uint32_t ExtFamily : 8; + uint32_t Reserved1 : 4; }; uint64_t raw; } EAX; @@ -96,10 +114,10 @@ namespace CPU { struct { - uint64_t BrandId : 8; - uint64_t CLFlush : 8; - uint64_t LogicalProcessorCount : 8; - uint64_t LocalApicId : 8; + uint32_t BrandId : 8; + uint32_t CLFlush : 8; + uint32_t LogicalProcessorCount : 8; + uint32_t LocalApicId : 8; }; uint64_t raw; } EBX; @@ -109,33 +127,33 @@ namespace CPU { struct { - uint64_t SSE3 : 1; - uint64_t PCLMULQDQ : 1; - uint64_t Reserved0 : 1; - uint64_t MONITOR : 1; - uint64_t Reserved1 : 5; - uint64_t SSSE3 : 1; - uint64_t Reserved2 : 2; - uint64_t FMA : 1; - uint64_t CMPXCHG16B : 1; - uint64_t Reserved3 : 5; - uint64_t SSE41 : 1; - uint64_t SSE42 : 1; - uint64_t x2APIC : 1; - uint64_t MOVBE : 1; - uint64_t POPCNT : 1; - uint64_t Reserved4 : 1; - uint64_t AES : 1; - uint64_t XSAVE : 1; - uint64_t OSXSAVE : 1; - uint64_t AVX : 1; - uint64_t F16C : 1; - uint64_t RDRAND : 1; + uint32_t SSE3 : 1; + uint32_t PCLMULQDQ : 1; + uint32_t Reserved0 : 1; + uint32_t MONITOR : 1; + uint32_t Reserved1 : 5; + uint32_t SSSE3 : 1; + uint32_t Reserved2 : 2; + uint32_t FMA : 1; + uint32_t CMPXCHG16B : 1; + uint32_t Reserved3 : 5; + uint32_t SSE41 : 1; + uint32_t SSE42 : 1; + uint32_t x2APIC : 1; + uint32_t MOVBE : 1; + uint32_t POPCNT : 1; + uint32_t Reserved4 : 1; + uint32_t AES : 1; + uint32_t XSAVE : 1; + uint32_t OSXSAVE : 1; + uint32_t AVX : 1; + uint32_t F16C : 1; + uint32_t RDRAND : 1; /** * @brief Reserved for use by hypervisor to indicate guest status. */ - uint64_t Hypervisor : 1; + uint32_t Hypervisor : 1; }; uint64_t raw; } ECX; @@ -145,34 +163,34 @@ namespace CPU { struct { - uint64_t FPU : 1; - uint64_t VME : 1; - uint64_t DE : 1; - uint64_t PSE : 1; - uint64_t TSC : 1; - uint64_t MSR : 1; - uint64_t PAE : 1; - uint64_t MCE : 1; - uint64_t CMPXCHG8B : 1; - uint64_t APIC : 1; - uint64_t Reserved0 : 1; - uint64_t SysEnterSysExit : 1; - uint64_t MTRR : 1; - uint64_t PGE : 1; - uint64_t MCA : 1; - uint64_t CMOV : 1; - uint64_t PAT : 1; - uint64_t PSE36 : 1; - uint64_t Reserved1 : 1; - uint64_t CLFSH : 1; - uint64_t Reserved2 : 3; - uint64_t MMX : 1; - uint64_t FXSR : 1; - uint64_t SSE : 1; - uint64_t SSE2 : 1; - uint64_t Reserved3 : 1; - uint64_t HTT : 1; - uint64_t Reserved4 : 3; + uint32_t FPU : 1; + uint32_t VME : 1; + uint32_t DE : 1; + uint32_t PSE : 1; + uint32_t TSC : 1; + uint32_t MSR : 1; + uint32_t PAE : 1; + uint32_t MCE : 1; + uint32_t CMPXCHG8B : 1; + uint32_t APIC : 1; + uint32_t Reserved0 : 1; + uint32_t SysEnterSysExit : 1; + uint32_t MTRR : 1; + uint32_t PGE : 1; + uint32_t MCA : 1; + uint32_t CMOV : 1; + uint32_t PAT : 1; + uint32_t PSE36 : 1; + uint32_t Reserved1 : 1; + uint32_t CLFSH : 1; + uint32_t Reserved2 : 3; + uint32_t MMX : 1; + uint32_t FXSR : 1; + uint32_t SSE : 1; + uint32_t SSE2 : 1; + uint32_t Reserved3 : 1; + uint32_t HTT : 1; + uint32_t Reserved4 : 3; }; uint64_t raw; } EDX; @@ -181,13 +199,22 @@ namespace CPU /** @brief Monitor and MWait Features */ struct CPUID0x00000005 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Monitor/MWait */ union { struct { - uint64_t MonLineSizeMin : 16; - uint64_t Reserved0 : 16; + uint32_t MonLineSizeMin : 16; + uint32_t Reserved0 : 16; }; uint64_t raw; } EAX; @@ -197,8 +224,8 @@ namespace CPU { struct { - uint64_t MonLineSizeMax : 16; - uint64_t Reserved0 : 16; + uint32_t MonLineSizeMax : 16; + uint32_t Reserved0 : 16; }; uint64_t raw; } EBX; @@ -208,9 +235,9 @@ namespace CPU { struct { - uint64_t EMX : 1; - uint64_t IBE : 1; - uint64_t Reserved0 : 30; + uint32_t EMX : 1; + uint32_t IBE : 1; + uint32_t Reserved0 : 30; }; uint64_t raw; } ECX; @@ -220,7 +247,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -229,14 +256,23 @@ namespace CPU /** @brief Power Management Related Features */ struct CPUID0x00000006 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Local APIC Timer Invariance */ union { struct { - uint64_t Reserved0 : 2; - uint64_t ARAT : 1; - uint64_t Reserved1 : 29; + uint32_t Reserved0 : 2; + uint32_t ARAT : 1; + uint32_t Reserved1 : 29; }; uint64_t raw; } EAX; @@ -246,7 +282,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -256,8 +292,8 @@ namespace CPU { struct { - uint64_t EffFreq : 1; - uint64_t Reserved0 : 31; + uint32_t EffFreq : 1; + uint32_t Reserved0 : 31; }; uint64_t raw; } ECX; @@ -267,7 +303,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -276,12 +312,21 @@ namespace CPU /** @brief Structured Extended Feature Identifiers */ struct CPUID0x00000007 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Structured Extended Feature Identifiers */ union { struct { - uint64_t MaxSubFn : 32; + uint32_t MaxSubFn : 32; }; uint64_t raw; } EAX; @@ -291,31 +336,31 @@ namespace CPU { struct { - uint64_t FSGSBASE : 1; - uint64_t Reserved0 : 2; - uint64_t BMI1 : 1; - uint64_t Reserved1 : 1; - uint64_t AVX2 : 1; - uint64_t Reserved2 : 1; - uint64_t SMEP : 1; - uint64_t BMI2 : 1; - uint64_t Reserved3 : 1; - uint64_t INVPCID : 1; - uint64_t Reserved4 : 1; - uint64_t PQM : 1; - uint64_t Reserved5 : 2; - uint64_t PQE : 1; - uint64_t Reserved6 : 2; - uint64_t RDSEED : 1; - uint64_t ADX : 1; - uint64_t SMAP : 1; - uint64_t Reserved7 : 1; - uint64_t RDPID : 1; - uint64_t CLFLUSHOPT : 1; - uint64_t CLWB : 1; - uint64_t Reserved8 : 4; - uint64_t SHA : 1; - uint64_t Reserved9 : 2; + uint32_t FSGSBASE : 1; + uint32_t Reserved0 : 2; + uint32_t BMI1 : 1; + uint32_t Reserved1 : 1; + uint32_t AVX2 : 1; + uint32_t Reserved2 : 1; + uint32_t SMEP : 1; + uint32_t BMI2 : 1; + uint32_t Reserved3 : 1; + uint32_t INVPCID : 1; + uint32_t Reserved4 : 1; + uint32_t PQM : 1; + uint32_t Reserved5 : 2; + uint32_t PQE : 1; + uint32_t Reserved6 : 2; + uint32_t RDSEED : 1; + uint32_t ADX : 1; + uint32_t SMAP : 1; + uint32_t Reserved7 : 1; + uint32_t RDPID : 1; + uint32_t CLFLUSHOPT : 1; + uint32_t CLWB : 1; + uint32_t Reserved8 : 4; + uint32_t SHA : 1; + uint32_t Reserved9 : 2; }; uint64_t raw; } EBX; @@ -325,18 +370,18 @@ namespace CPU { struct { - uint64_t Reserved0 : 2; - uint64_t UMIP : 1; - uint64_t PKU : 1; - uint64_t OSPKE : 1; - uint64_t Reserved1 : 2; - uint64_t CET_SS : 1; - uint64_t Reserved2 : 1; - uint64_t VAES : 1; - uint64_t VPCLMULQDQ : 1; - uint64_t Reserved3 : 5; - uint64_t LA57 : 1; - uint64_t Reserved4 : 15; + uint32_t Reserved0 : 2; + uint32_t UMIP : 1; + uint32_t PKU : 1; + uint32_t OSPKE : 1; + uint32_t Reserved1 : 2; + uint32_t CET_SS : 1; + uint32_t Reserved2 : 1; + uint32_t VAES : 1; + uint32_t VPCLMULQDQ : 1; + uint32_t Reserved3 : 5; + uint32_t LA57 : 1; + uint32_t Reserved4 : 15; }; uint64_t raw; } ECX; @@ -346,7 +391,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -355,13 +400,22 @@ namespace CPU /** @brief Thread Level - Extended Topology Enumeration */ struct CPUID0x0000000B_ECX_0 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Extended Topology Enumeration */ union { struct { - uint64_t ThreadMaskWidth : 5; - uint64_t Reserved0 : 27; + uint32_t ThreadMaskWidth : 5; + uint32_t Reserved0 : 27; }; uint64_t raw; } EAX; @@ -371,8 +425,8 @@ namespace CPU { struct { - uint64_t NumberOfThreadsInACore : 5; /* No field name */ - uint64_t Reserved0 : 27; + uint32_t NumberOfThreadsInACore : 5; /* No field name */ + uint32_t Reserved0 : 27; }; uint64_t raw; } EBX; @@ -382,9 +436,9 @@ namespace CPU { struct { - uint64_t ECXInputValue : 8; - uint64_t LevelNumber : 8; - uint64_t Reserved0 : 16; + uint32_t ECXInputValue : 8; + uint32_t LevelNumber : 8; + uint32_t Reserved0 : 16; }; uint64_t raw; } ECX; @@ -394,7 +448,7 @@ namespace CPU { struct { - uint64_t x2APID_ID : 32; + uint32_t x2APID_ID : 32; }; uint64_t raw; } EDX; @@ -403,13 +457,22 @@ namespace CPU /** @brief Core Level - Extended Topology Enumeration */ struct CPUID0x0000000B_ECX_1 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Extended Topology Enumeration */ union { struct { - uint64_t CoreMaskWidth : 5; - uint64_t Reserved0 : 27; + uint32_t CoreMaskWidth : 5; + uint32_t Reserved0 : 27; }; uint64_t raw; } EAX; @@ -419,8 +482,8 @@ namespace CPU { struct { - uint64_t NumberOfLogicalCoresInSocket : 5; /* No field name */ - uint64_t Reserved0 : 27; + uint32_t NumberOfLogicalCoresInSocket : 5; /* No field name */ + uint32_t Reserved0 : 27; }; uint64_t raw; } EBX; @@ -430,9 +493,9 @@ namespace CPU { struct { - uint64_t ECXInputValue : 8; - uint64_t LevelNumber : 8; - uint64_t Reserved0 : 16; + uint32_t ECXInputValue : 8; + uint32_t LevelNumber : 8; + uint32_t Reserved0 : 16; }; uint64_t raw; } ECX; @@ -442,7 +505,7 @@ namespace CPU { struct { - uint64_t x2APID_ID : 32; + uint32_t x2APID_ID : 32; }; uint64_t raw; } EDX; @@ -451,12 +514,21 @@ namespace CPU /** @brief Processor Extended State Enumeration */ struct CPUID0x0000000D_ECX_0 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Processor Extended State Enumeration */ union { struct { - uint64_t XFeatureSupportedMask : 32; + uint32_t XFeatureSupportedMask : 32; }; uint64_t raw; } EAX; @@ -466,7 +538,7 @@ namespace CPU { struct { - uint64_t XFeatureEnabledSizeMax : 32; + uint32_t XFeatureEnabledSizeMax : 32; }; uint64_t raw; } EBX; @@ -476,7 +548,7 @@ namespace CPU { struct { - uint64_t XFeatureSupportedSizeMax : 32; + uint32_t XFeatureSupportedSizeMax : 32; }; uint64_t raw; } ECX; @@ -486,7 +558,7 @@ namespace CPU { struct { - uint64_t XFeatureSupportedMask : 32; + uint32_t XFeatureSupportedMask : 32; }; uint64_t raw; } EDX; @@ -495,16 +567,25 @@ namespace CPU /** @brief Processor Extended State Enumeration */ struct CPUID0x0000000D_ECX_1 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Processor Extended State Enumeration */ union { struct { - uint64_t XSAVEOPT : 1; - uint64_t XSAVEC : 1; - uint64_t XGETBV : 1; - uint64_t XSAVES : 1; - uint64_t Reserved0 : 28; + uint32_t XSAVEOPT : 1; + uint32_t XSAVEC : 1; + uint32_t XGETBV : 1; + uint32_t XSAVES : 1; + uint32_t Reserved0 : 28; }; uint64_t raw; } EAX; @@ -524,7 +605,7 @@ namespace CPU * + ((XSS[CET_U] == 1) ? 0000_0010h : 0) * + ((XSS[CET_S] == 1) ? 0000_0018h : 0) */ - uint64_t ebx : 32; + uint32_t ebx : 32; }; uint64_t raw; } EBX; @@ -534,10 +615,10 @@ namespace CPU { struct { - uint64_t Reserved0 : 11; - uint64_t CET_U : 1; - uint64_t CET_S : 1; - uint64_t Reserved1 : 19; + uint32_t Reserved0 : 11; + uint32_t CET_U : 1; + uint32_t CET_S : 1; + uint32_t Reserved1 : 19; }; uint64_t raw; } ECX; @@ -547,7 +628,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -556,12 +637,21 @@ namespace CPU /** @brief Processor Extended State Enumeration */ struct CPUID0x0000000D_ECX_2 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Processor Extended State Enumeration */ union { struct { - uint64_t YmmSaveStateSize : 32; + uint32_t YmmSaveStateSize : 32; }; uint64_t raw; } EAX; @@ -571,7 +661,7 @@ namespace CPU { struct { - uint64_t YmmSaveStateOffset : 32; + uint32_t YmmSaveStateOffset : 32; }; uint64_t raw; } EBX; @@ -581,7 +671,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -591,7 +681,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -600,12 +690,21 @@ namespace CPU /** @brief Processor Extended State Emulation */ struct CPUID0x0000000D_ECX_11 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Processor Extended State Emulation */ union { struct { - uint64_t CetSupervisorSize : 32; + uint32_t CetSupervisorSize : 32; }; uint64_t raw; } EAX; @@ -615,7 +714,7 @@ namespace CPU { struct { - uint64_t CetSupervisorOffset : 32; + uint32_t CetSupervisorOffset : 32; }; uint64_t raw; } EBX; @@ -625,8 +724,8 @@ namespace CPU { struct { - uint64_t Reserved : 31; - uint64_t US : 1; + uint32_t Reserved : 31; + uint32_t US : 1; }; uint64_t raw; } ECX; @@ -636,7 +735,7 @@ namespace CPU { struct { - uint64_t Unused : 32; + uint32_t Unused : 32; }; uint64_t raw; } EDX; @@ -645,12 +744,21 @@ namespace CPU /** @brief Processor Extended State Enumeration */ struct CPUID0x0000000D_ECX_3H { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Processor Extended State Enumeration */ union { struct { - uint64_t LwpSaveStateSize : 32; + uint32_t LwpSaveStateSize : 32; }; uint64_t raw; } EAX; @@ -660,7 +768,7 @@ namespace CPU { struct { - uint64_t LwpSaveStateOffset : 32; + uint32_t LwpSaveStateOffset : 32; }; uint64_t raw; } EBX; @@ -670,7 +778,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -680,7 +788,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -689,12 +797,21 @@ namespace CPU /** @brief Maximum Extended Function Number and Vendor String */ struct CPUID0x80000000 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Largest Extended Function Number */ union { struct { - uint64_t LFuncExt : 32; + uint32_t LFuncExt : 32; }; uint64_t raw; } EAX; @@ -733,19 +850,28 @@ namespace CPU /** @brief Extended Processor and Processor Feature Identifiers */ struct CPUID0x80000001 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief AMD Family, Model, Stepping */ union { /* "This function is an identical copy of CPUID Fn0000_0001_EAX." */ struct { - uint64_t Stepping : 4; - uint64_t BaseModel : 4; - uint64_t BaseFamily : 4; - uint64_t Reserved0 : 4; - uint64_t ExtendedModel : 4; - uint64_t ExtendedFamily : 8; - uint64_t Reserved1 : 4; + uint32_t Stepping : 4; + uint32_t BaseModel : 4; + uint32_t BaseFamily : 4; + uint32_t Reserved0 : 4; + uint32_t ExtendedModel : 4; + uint32_t ExtendedFamily : 8; + uint32_t Reserved1 : 4; }; uint64_t raw; } EAX; @@ -755,9 +881,9 @@ namespace CPU { struct { - uint64_t BrandId : 16; - uint64_t Reserved0 : 12; - uint64_t PkgType : 4; + uint32_t BrandId : 16; + uint32_t Reserved0 : 12; + uint32_t PkgType : 4; }; uint64_t raw; } EBX; @@ -767,36 +893,36 @@ namespace CPU { struct { - uint64_t LahfSahf : 1; - uint64_t CmpLegacy : 1; - uint64_t SVM : 1; - uint64_t ExtApicSpace : 1; - uint64_t AltMovCr8 : 1; - uint64_t ABM : 1; - uint64_t SSE4A : 1; - uint64_t MisAlignSse : 1; - uint64_t ThreeDNowPrefetch : 1; - uint64_t OSVW : 1; - uint64_t IBS : 1; - uint64_t XOP : 1; - uint64_t SKINIT : 1; - uint64_t WDT : 1; - uint64_t Reserved0 : 1; - uint64_t LWP : 1; - uint64_t FMA4 : 1; - uint64_t TCE : 1; - uint64_t Reserved1 : 3; - uint64_t TBM : 1; - uint64_t TopologyExtensions : 1; - uint64_t PerfCtrExtCore : 1; - uint64_t PerfCtrExtNB : 1; - uint64_t Reserved2 : 1; - uint64_t DataBkptExt : 1; - uint64_t PerfTsc : 1; - uint64_t PerfCtrExtLLC : 1; - uint64_t MONITORX : 1; - uint64_t AddrMaskExt : 1; - uint64_t Reserved3 : 1; + uint32_t LahfSahf : 1; + uint32_t CmpLegacy : 1; + uint32_t SVM : 1; + uint32_t ExtApicSpace : 1; + uint32_t AltMovCr8 : 1; + uint32_t ABM : 1; + uint32_t SSE4A : 1; + uint32_t MisAlignSse : 1; + uint32_t ThreeDNowPrefetch : 1; + uint32_t OSVW : 1; + uint32_t IBS : 1; + uint32_t XOP : 1; + uint32_t SKINIT : 1; + uint32_t WDT : 1; + uint32_t Reserved0 : 1; + uint32_t LWP : 1; + uint32_t FMA4 : 1; + uint32_t TCE : 1; + uint32_t Reserved1 : 3; + uint32_t TBM : 1; + uint32_t TopologyExtensions : 1; + uint32_t PerfCtrExtCore : 1; + uint32_t PerfCtrExtNB : 1; + uint32_t Reserved2 : 1; + uint32_t DataBkptExt : 1; + uint32_t PerfTsc : 1; + uint32_t PerfCtrExtLLC : 1; + uint32_t MONITORX : 1; + uint32_t AddrMaskExt : 1; + uint32_t Reserved3 : 1; }; uint64_t raw; } ECX; @@ -806,37 +932,37 @@ namespace CPU { struct { - uint64_t FPU : 1; - uint64_t VME : 1; - uint64_t DE : 1; - uint64_t PSE : 1; - uint64_t TSC : 1; - uint64_t MSR : 1; - uint64_t PAE : 1; - uint64_t MCE : 1; - uint64_t CMPXCHG8B : 1; - uint64_t APIC : 1; - uint64_t Reserved0 : 1; - uint64_t SysCallSysRet : 1; - uint64_t MTRR : 1; - uint64_t PGE : 1; - uint64_t MCA : 1; - uint64_t CMOV : 1; - uint64_t PAT : 1; - uint64_t PSE36 : 1; - uint64_t Reserved1 : 2; - uint64_t NX : 1; - uint64_t Reserved2 : 1; - uint64_t MmxExt : 1; - uint64_t MMX : 1; - uint64_t FXSR : 1; - uint64_t FFXSR : 1; - uint64_t Page1GB : 1; - uint64_t RDTSCP : 1; - uint64_t Reserved3 : 1; - uint64_t LM : 1; - uint64_t ThreeDNowExtended : 1; - uint64_t ThreeDNow : 1; + uint32_t FPU : 1; + uint32_t VME : 1; + uint32_t DE : 1; + uint32_t PSE : 1; + uint32_t TSC : 1; + uint32_t MSR : 1; + uint32_t PAE : 1; + uint32_t MCE : 1; + uint32_t CMPXCHG8B : 1; + uint32_t APIC : 1; + uint32_t Reserved0 : 1; + uint32_t SysCallSysRet : 1; + uint32_t MTRR : 1; + uint32_t PGE : 1; + uint32_t MCA : 1; + uint32_t CMOV : 1; + uint32_t PAT : 1; + uint32_t PSE36 : 1; + uint32_t Reserved1 : 2; + uint32_t NX : 1; + uint32_t Reserved2 : 1; + uint32_t MmxExt : 1; + uint32_t MMX : 1; + uint32_t FXSR : 1; + uint32_t FFXSR : 1; + uint32_t Page1GB : 1; + uint32_t RDTSCP : 1; + uint32_t Reserved3 : 1; + uint32_t LM : 1; + uint32_t ThreeDNowExtended : 1; + uint32_t ThreeDNow : 1; }; uint64_t raw; } EDX; @@ -845,6 +971,15 @@ namespace CPU /** @brief Extended Processor Name String */ struct CPUID0x80000002 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -885,6 +1020,15 @@ namespace CPU /** @brief Extended Processor Name String */ struct CPUID0x80000003 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -925,6 +1069,15 @@ namespace CPU /** @brief Extended Processor Name String */ struct CPUID0x80000004 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -965,15 +1118,24 @@ namespace CPU /** @brief L1 Cache and TLB Information */ struct CPUID0x80000005 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief L1 TLB 2M/4M Information */ union { struct { - uint64_t L1ITlb2and4MSize : 8; - uint64_t L1ITlb2and4MAssoc : 8; - uint64_t L1DTlb2and4MSize : 8; - uint64_t L1DTlb2and4MAssoc : 8; + uint32_t L1ITlb2and4MSize : 8; + uint32_t L1ITlb2and4MAssoc : 8; + uint32_t L1DTlb2and4MSize : 8; + uint32_t L1DTlb2and4MAssoc : 8; }; uint64_t raw; } EAX; @@ -983,10 +1145,10 @@ namespace CPU { struct { - uint64_t L1ITlb4KSize : 8; - uint64_t L1ITlb4KAssoc : 8; - uint64_t L1DTlb4KSize : 8; - uint64_t L1DTlb4KAssoc : 8; + uint32_t L1ITlb4KSize : 8; + uint32_t L1ITlb4KAssoc : 8; + uint32_t L1DTlb4KSize : 8; + uint32_t L1DTlb4KAssoc : 8; }; uint64_t raw; } EBX; @@ -996,10 +1158,10 @@ namespace CPU { struct { - uint64_t L1DcLineSize : 8; - uint64_t L1DcLinesPerTag : 8; - uint64_t L1DcAssoc : 8; - uint64_t L1DcSize : 8; + uint32_t L1DcLineSize : 8; + uint32_t L1DcLinesPerTag : 8; + uint32_t L1DcAssoc : 8; + uint32_t L1DcSize : 8; }; uint64_t raw; } ECX; @@ -1009,10 +1171,10 @@ namespace CPU { struct { - uint64_t L1IcLineSize : 8; - uint64_t L1IcLinesPerTag : 8; - uint64_t L1IcAssoc : 8; - uint64_t L1IcSize : 8; + uint32_t L1IcLineSize : 8; + uint32_t L1IcLinesPerTag : 8; + uint32_t L1IcAssoc : 8; + uint32_t L1IcSize : 8; }; uint64_t raw; } EDX; @@ -1021,15 +1183,24 @@ namespace CPU /** @brief L2 Cache and TLB and L3 Cache Information */ struct CPUID0x80000006 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief L2 TLB 2M/4M Information */ union { struct { - uint64_t L2ITlb2and4MSize : 12; - uint64_t L2ITlb2and4MAssoc : 4; - uint64_t L2DTlb2and4MSize : 12; - uint64_t L2DTlb2and4MAssoc : 4; + uint32_t L2ITlb2and4MSize : 12; + uint32_t L2ITlb2and4MAssoc : 4; + uint32_t L2DTlb2and4MSize : 12; + uint32_t L2DTlb2and4MAssoc : 4; }; uint64_t raw; } EAX; @@ -1039,10 +1210,10 @@ namespace CPU { struct { - uint64_t L2ITlb4KSize : 12; - uint64_t L2ITlb4KAssoc : 4; - uint64_t L2DTlb4KSize : 12; - uint64_t L2DTlb4KAssoc : 4; + uint32_t L2ITlb4KSize : 12; + uint32_t L2ITlb4KAssoc : 4; + uint32_t L2DTlb4KSize : 12; + uint32_t L2DTlb4KAssoc : 4; }; uint64_t raw; } EBX; @@ -1052,10 +1223,10 @@ namespace CPU { struct { - uint64_t L2LineSize : 8; - uint64_t L2LinesPerTag : 4; - uint64_t L2Assoc : 4; - uint64_t L2Size : 16; + uint32_t L2LineSize : 8; + uint32_t L2LinesPerTag : 4; + uint32_t L2Assoc : 4; + uint32_t L2Size : 16; }; uint64_t raw; } ECX; @@ -1065,11 +1236,11 @@ namespace CPU { struct { - uint64_t L3LineSize : 8; - uint64_t L3LinesPerTag : 4; - uint64_t L3Assoc : 4; - uint64_t Reserved0 : 2; - uint64_t L3Size : 14; + uint32_t L3LineSize : 8; + uint32_t L3LinesPerTag : 4; + uint32_t L3Assoc : 4; + uint32_t Reserved0 : 2; + uint32_t L3Size : 14; }; uint64_t raw; } EDX; @@ -1078,11 +1249,20 @@ namespace CPU /** @brief Processor Power Management and RAS Capabilities */ struct CPUID0x80000007 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EAX; @@ -1092,11 +1272,11 @@ namespace CPU { struct { - uint64_t McaOverflowRecov : 1; - uint64_t SUCCOR : 1; - uint64_t HWA : 1; - uint64_t ScalableMca : 1; - uint64_t Reserved0 : 28; + uint32_t McaOverflowRecov : 1; + uint32_t SUCCOR : 1; + uint32_t HWA : 1; + uint32_t ScalableMca : 1; + uint32_t Reserved0 : 28; }; uint64_t raw; } EBX; @@ -1106,7 +1286,7 @@ namespace CPU { struct { - uint64_t CpuPwrSampleTimeRatio : 32; + uint32_t CpuPwrSampleTimeRatio : 32; }; uint64_t raw; } ECX; @@ -1116,20 +1296,20 @@ namespace CPU { struct { - uint64_t TS : 1; - uint64_t FID : 1; - uint64_t VID : 1; - uint64_t TTP : 1; - uint64_t TM : 1; - uint64_t Reserved0 : 1; - uint64_t OneHundredMHzSteps : 1; - uint64_t HwPstate : 1; - uint64_t TscInvariant : 1; - uint64_t CPB : 1; - uint64_t EffFreqRO : 1; - uint64_t ProcFeedbackInterface : 1; - uint64_t ProcPowerReporting : 1; - uint64_t Reserved1 : 19; + uint32_t TS : 1; + uint32_t FID : 1; + uint32_t VID : 1; + uint32_t TTP : 1; + uint32_t TM : 1; + uint32_t Reserved0 : 1; + uint32_t OneHundredMHzSteps : 1; + uint32_t HwPstate : 1; + uint32_t TscInvariant : 1; + uint32_t CPB : 1; + uint32_t EffFreqRO : 1; + uint32_t ProcFeedbackInterface : 1; + uint32_t ProcPowerReporting : 1; + uint32_t Reserved1 : 19; }; uint64_t raw; } EDX; @@ -1138,15 +1318,24 @@ namespace CPU /** @brief Processor Capacity Parameters and Extended Feature Identification */ struct CPUID0x80000008 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief Long Mode Size Identifiers */ union { struct { - uint64_t PhysAddrSize : 8; - uint64_t LinAddrSize : 8; - uint64_t GuestPhysAddrSize : 8; - uint64_t Reserved0 : 8; + uint32_t PhysAddrSize : 8; + uint32_t LinAddrSize : 8; + uint32_t GuestPhysAddrSize : 8; + uint32_t Reserved0 : 8; }; uint64_t raw; } EAX; @@ -1156,33 +1345,33 @@ namespace CPU { struct { - uint64_t CLZERO : 1; - uint64_t InstRetCntMsr : 1; - uint64_t RstrFpErrPtrs : 1; - uint64_t INVLPGB : 1; - uint64_t RDPRU : 1; - uint64_t Reserved0 : 3; - uint64_t MCOMMIT : 1; - uint64_t WBNOINVD : 1; - uint64_t Reserved1 : 2; - uint64_t IBPB : 1; - uint64_t INT_WBINVD : 1; - uint64_t IBRS : 1; - uint64_t STIBP : 1; - uint64_t IbrsAlwaysOn : 1; - uint64_t StibpAlwaysOn : 1; - uint64_t IbrsPreferred : 1; - uint64_t IbrsSameMode : 1; - uint64_t EferLmsleUnsupported : 1; - uint64_t INVLPGBnestedPages : 1; - uint64_t Reserved2 : 2; - uint64_t SSBD : 1; - uint64_t SsbdVirtSpecCtrl : 1; - uint64_t SsbdNotRequired : 1; - uint64_t Reserved3 : 1; - uint64_t PSFD : 1; - uint64_t BTC_NO : 1; - uint64_t Reserved4 : 2; + uint32_t CLZERO : 1; + uint32_t InstRetCntMsr : 1; + uint32_t RstrFpErrPtrs : 1; + uint32_t INVLPGB : 1; + uint32_t RDPRU : 1; + uint32_t Reserved0 : 3; + uint32_t MCOMMIT : 1; + uint32_t WBNOINVD : 1; + uint32_t Reserved1 : 2; + uint32_t IBPB : 1; + uint32_t INT_WBINVD : 1; + uint32_t IBRS : 1; + uint32_t STIBP : 1; + uint32_t IbrsAlwaysOn : 1; + uint32_t StibpAlwaysOn : 1; + uint32_t IbrsPreferred : 1; + uint32_t IbrsSameMode : 1; + uint32_t EferLmsleUnsupported : 1; + uint32_t INVLPGBnestedPages : 1; + uint32_t Reserved2 : 2; + uint32_t SSBD : 1; + uint32_t SsbdVirtSpecCtrl : 1; + uint32_t SsbdNotRequired : 1; + uint32_t Reserved3 : 1; + uint32_t PSFD : 1; + uint32_t BTC_NO : 1; + uint32_t Reserved4 : 2; }; uint64_t raw; } EBX; @@ -1192,11 +1381,11 @@ namespace CPU { struct { - uint64_t NT : 8; - uint64_t Reserved0 : 4; - uint64_t ApicIdSize : 4; - uint64_t PerfTscSize : 2; - uint64_t Reserved1 : 14; + uint32_t NT : 8; + uint32_t Reserved0 : 4; + uint32_t ApicIdSize : 4; + uint32_t PerfTscSize : 2; + uint32_t Reserved1 : 14; }; uint64_t raw; } ECX; @@ -1206,8 +1395,8 @@ namespace CPU { struct { - uint64_t InvlpgbCountMax : 16; - uint64_t MaxRdpruID : 16; + uint32_t InvlpgbCountMax : 16; + uint32_t MaxRdpruID : 16; }; uint64_t raw; } EDX; @@ -1216,12 +1405,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000000A { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1231,7 +1429,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1241,7 +1439,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1251,7 +1449,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1260,12 +1458,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000019 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1275,7 +1482,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1285,7 +1492,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1295,7 +1502,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1304,12 +1511,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001A { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1319,7 +1535,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1329,7 +1545,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1339,7 +1555,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1348,12 +1564,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001B { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1363,7 +1588,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1373,7 +1598,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1383,7 +1608,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1392,12 +1617,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001C { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1407,7 +1641,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1417,7 +1651,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1427,7 +1661,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1436,12 +1670,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001D { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1451,7 +1694,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1461,7 +1704,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1471,7 +1714,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1480,12 +1723,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001E { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1495,7 +1747,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1505,7 +1757,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1515,7 +1767,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1524,12 +1776,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x8000001F { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1539,7 +1800,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1549,7 +1810,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1559,7 +1820,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1568,12 +1829,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000020 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1583,7 +1853,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1593,7 +1863,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1603,7 +1873,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1612,12 +1882,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000021 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1627,7 +1906,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1637,7 +1916,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1647,7 +1926,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1656,12 +1935,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000022 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1671,7 +1959,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1681,7 +1969,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1691,7 +1979,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1700,12 +1988,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000023 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1715,7 +2012,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1725,7 +2022,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1735,7 +2032,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1744,12 +2041,21 @@ namespace CPU /** @brief TODO */ struct CPUID0x80000026 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + /** @brief */ union { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EAX; @@ -1759,7 +2065,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EBX; @@ -1769,7 +2075,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } ECX; @@ -1779,7 +2085,7 @@ namespace CPU { struct { - uint64_t todo : 32; + uint32_t todo : 32; }; uint64_t raw; } EDX; @@ -1788,4 +2094,4 @@ namespace CPU } } -#endif // !__FENNIX_KERNEL_CPU_x64_CPUID_AMD_H__ +#endif // !__FENNIX_KERNEL_CPU_x86_CPUID_AMD_H__ diff --git a/include/cpu/x86/x64/cpuid_intel.hpp b/include/cpu/x86/cpuid_intel.hpp similarity index 55% rename from include/cpu/x86/x64/cpuid_intel.hpp rename to include/cpu/x86/cpuid_intel.hpp index ce37fb2..2a8e521 100644 --- a/include/cpu/x86/x64/cpuid_intel.hpp +++ b/include/cpu/x86/cpuid_intel.hpp @@ -15,14 +15,14 @@ along with Fennix Kernel. If not, see . */ -#ifndef __FENNIX_KERNEL_CPU_x64_CPUID_INTEL_H__ -#define __FENNIX_KERNEL_CPU_x64_CPUID_INTEL_H__ +#ifndef __FENNIX_KERNEL_CPU_x86_CPUID_INTEL_H__ +#define __FENNIX_KERNEL_CPU_x86_CPUID_INTEL_H__ #include namespace CPU { - namespace x64 + namespace x86 { /** @brief EXPERIMENTAL IMPLEMENTATION */ namespace Intel @@ -30,11 +30,20 @@ namespace CPU /** @brief Basic CPU information */ struct CPUID0x00000000 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t HighestFunctionSupported : 32; + uint32_t HighestFunctionSupported : 32; }; uint64_t raw; } EAX; @@ -67,18 +76,27 @@ namespace CPU /** @brief Additional CPU information */ struct CPUID0x00000001 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t SteppingID : 4; - uint64_t ModelID : 4; - uint64_t FamilyID : 4; - uint64_t Type : 2; - uint64_t Reserved0 : 2; - uint64_t ExtendedModel : 4; - uint64_t ExtendedFamily : 8; - uint64_t Reserved1 : 4; + uint32_t SteppingID : 4; + uint32_t ModelID : 4; + uint32_t FamilyID : 4; + uint32_t Type : 2; + uint32_t Reserved0 : 2; + uint32_t ExtendedModel : 4; + uint32_t ExtendedFamily : 8; + uint32_t Reserved1 : 4; }; uint64_t raw; } EAX; @@ -87,10 +105,10 @@ namespace CPU { struct { - uint64_t BrandIndex : 8; - uint64_t CLFLUSHLineSize : 8; - uint64_t LogicalProcessorsPerPackage : 8; - uint64_t LocalAPICID : 8; + uint32_t BrandIndex : 8; + uint32_t CLFLUSHLineSize : 8; + uint32_t LogicalProcessorsPerPackage : 8; + uint32_t LocalAPICID : 8; }; uint64_t raw; } EBX; @@ -99,39 +117,39 @@ namespace CPU { struct { - uint64_t SSE3 : 1; - uint64_t PCLMULQDQ : 1; - uint64_t DTES64 : 1; - uint64_t MONITOR : 1; - uint64_t DS_CPL : 1; - uint64_t VMX : 1; - uint64_t SMX : 1; - uint64_t EIST : 1; - uint64_t TM2 : 1; - uint64_t SSSE3 : 1; - uint64_t CNXT_ID : 1; - uint64_t Reserved0 : 1; - uint64_t FMA : 1; - uint64_t CMPXCHG16B : 1; - uint64_t xTPRUpdateControl : 1; - uint64_t PDCM : 1; - uint64_t Reserved1 : 1; - uint64_t PCID : 1; - uint64_t DCA : 1; - uint64_t SSE4_1 : 1; - uint64_t SSE4_2 : 1; - uint64_t x2APIC : 1; - uint64_t MOVBE : 1; - uint64_t POPCNT : 1; - uint64_t TSCDeadline : 1; - uint64_t AES : 1; - uint64_t XSAVE : 1; - uint64_t OSXSAVE : 1; - uint64_t AVX : 1; - uint64_t F16C : 1; - uint64_t RDRAND : 1; - uint64_t Reserved2 : 1; - uint64_t Hypervisor : 1; + uint32_t SSE3 : 1; + uint32_t PCLMULQDQ : 1; + uint32_t DTES64 : 1; + uint32_t MONITOR : 1; + uint32_t DS_CPL : 1; + uint32_t VMX : 1; + uint32_t SMX : 1; + uint32_t EIST : 1; + uint32_t TM2 : 1; + uint32_t SSSE3 : 1; + uint32_t CNXT_ID : 1; + uint32_t Reserved0 : 1; + uint32_t FMA : 1; + uint32_t CMPXCHG16B : 1; + uint32_t xTPRUpdateControl : 1; + uint32_t PDCM : 1; + uint32_t Reserved1 : 1; + uint32_t PCID : 1; + uint32_t DCA : 1; + uint32_t SSE4_1 : 1; + uint32_t SSE4_2 : 1; + uint32_t x2APIC : 1; + uint32_t MOVBE : 1; + uint32_t POPCNT : 1; + uint32_t TSCDeadline : 1; + uint32_t AES : 1; + uint32_t XSAVE : 1; + uint32_t OSXSAVE : 1; + uint32_t AVX : 1; + uint32_t F16C : 1; + uint32_t RDRAND : 1; + uint32_t Reserved2 : 1; + uint32_t Hypervisor : 1; }; uint64_t raw; } ECX; @@ -140,38 +158,38 @@ namespace CPU { struct { - uint64_t FPU : 1; - uint64_t VME : 1; - uint64_t DE : 1; - uint64_t PSE : 1; - uint64_t TSC : 1; - uint64_t MSR : 1; - uint64_t PAE : 1; - uint64_t MCE : 1; - uint64_t CX8 : 1; - uint64_t APIC : 1; - uint64_t Reserved0 : 1; - uint64_t SEP : 1; - uint64_t MTRR : 1; - uint64_t PGE : 1; - uint64_t MCA : 1; - uint64_t CMOV : 1; - uint64_t PAT : 1; - uint64_t PSE36 : 1; - uint64_t PSN : 1; - uint64_t CLFSH : 1; - uint64_t Reserved1 : 1; - uint64_t DS : 1; - uint64_t ACPI : 1; - uint64_t MMX : 1; - uint64_t FXSR : 1; - uint64_t SSE : 1; - uint64_t SSE2 : 1; - uint64_t SS : 1; - uint64_t HTT : 1; - uint64_t TM : 1; - uint64_t Reserved2 : 1; - uint64_t PBE : 1; + uint32_t FPU : 1; + uint32_t VME : 1; + uint32_t DE : 1; + uint32_t PSE : 1; + uint32_t TSC : 1; + uint32_t MSR : 1; + uint32_t PAE : 1; + uint32_t MCE : 1; + uint32_t CX8 : 1; + uint32_t APIC : 1; + uint32_t Reserved0 : 1; + uint32_t SEP : 1; + uint32_t MTRR : 1; + uint32_t PGE : 1; + uint32_t MCA : 1; + uint32_t CMOV : 1; + uint32_t PAT : 1; + uint32_t PSE36 : 1; + uint32_t PSN : 1; + uint32_t CLFSH : 1; + uint32_t Reserved1 : 1; + uint32_t DS : 1; + uint32_t ACPI : 1; + uint32_t MMX : 1; + uint32_t FXSR : 1; + uint32_t SSE : 1; + uint32_t SSE2 : 1; + uint32_t SS : 1; + uint32_t HTT : 1; + uint32_t TM : 1; + uint32_t Reserved2 : 1; + uint32_t PBE : 1; }; uint64_t raw; } EDX; @@ -180,14 +198,23 @@ namespace CPU /** @brief CPU cache and TLB */ struct CPUID0x00000002 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t CacheLineSize : 8; - uint64_t CacheLinesPerTag : 8; - uint64_t Associativity : 8; - uint64_t CacheSize : 8; + uint32_t CacheLineSize : 8; + uint32_t CacheLinesPerTag : 8; + uint32_t Associativity : 8; + uint32_t CacheSize : 8; }; uint64_t raw; } EAX; @@ -196,10 +223,10 @@ namespace CPU { struct { - uint64_t CacheLineSize : 8; - uint64_t CacheLinesPerTag : 8; - uint64_t Associativity : 8; - uint64_t CacheSize : 8; + uint32_t CacheLineSize : 8; + uint32_t CacheLinesPerTag : 8; + uint32_t Associativity : 8; + uint32_t CacheSize : 8; }; uint64_t raw; } EBX; @@ -208,10 +235,10 @@ namespace CPU { struct { - uint64_t CacheLineSize : 8; - uint64_t CacheLinesPerTag : 8; - uint64_t Associativity : 8; - uint64_t CacheSize : 8; + uint32_t CacheLineSize : 8; + uint32_t CacheLinesPerTag : 8; + uint32_t Associativity : 8; + uint32_t CacheSize : 8; }; uint64_t raw; } ECX; @@ -220,10 +247,10 @@ namespace CPU { struct { - uint64_t CacheLineSize : 8; - uint64_t CacheLinesPerTag : 8; - uint64_t Associativity : 8; - uint64_t CacheSize : 8; + uint32_t CacheLineSize : 8; + uint32_t CacheLinesPerTag : 8; + uint32_t Associativity : 8; + uint32_t CacheSize : 8; }; uint64_t raw; } EDX; @@ -232,11 +259,20 @@ namespace CPU /** @brief CPU serial number */ struct CPUID0x00000003 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EAX; @@ -245,7 +281,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -254,7 +290,7 @@ namespace CPU { struct { - uint64_t ProcessorSerialNumber : 32; + uint32_t ProcessorSerialNumber : 32; }; uint64_t raw; } ECX; @@ -263,7 +299,7 @@ namespace CPU { struct { - uint64_t ProcessorSerialNumber : 32; + uint32_t ProcessorSerialNumber : 32; }; uint64_t raw; } EDX; @@ -272,17 +308,26 @@ namespace CPU /** @brief Cache information */ struct CPUID0x00000004_1 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Type : 5; - uint64_t Level : 3; - uint64_t SelfInitializing : 1; - uint64_t FullyAssociative : 1; - uint64_t Reserved : 4; - uint64_t MaxAddressableIdsForLogicalProcessors : 12; - uint64_t CoresPerPackage : 6; + uint32_t Type : 5; + uint32_t Level : 3; + uint32_t SelfInitializing : 1; + uint32_t FullyAssociative : 1; + uint32_t Reserved : 4; + uint32_t MaxAddressableIdsForLogicalProcessors : 12; + uint32_t CoresPerPackage : 6; }; uint64_t raw; } EAX; @@ -291,9 +336,9 @@ namespace CPU { struct { - uint64_t SystemCoherencyLineSize : 12; - uint64_t PhysicalLinePartitions : 10; - uint64_t WaysOfAssociativity : 10; + uint32_t SystemCoherencyLineSize : 12; + uint32_t PhysicalLinePartitions : 10; + uint32_t WaysOfAssociativity : 10; }; uint64_t raw; } EBX; @@ -302,7 +347,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -311,7 +356,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -320,12 +365,21 @@ namespace CPU /** @brief MONITOR information */ struct CPUID0x00000005 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t SmallestMonitorLineSize : 16; - uint64_t Reserved : 16; + uint32_t SmallestMonitorLineSize : 16; + uint32_t Reserved : 16; }; uint64_t raw; } EAX; @@ -334,8 +388,8 @@ namespace CPU { struct { - uint64_t LargestMonitorLineSize : 16; - uint64_t Reserved : 16; + uint32_t LargestMonitorLineSize : 16; + uint32_t Reserved : 16; }; uint64_t raw; } EBX; @@ -344,9 +398,9 @@ namespace CPU { struct { - uint64_t MWAITEnumerationSupported : 1; - uint64_t InterruptsAsBreakEvent : 1; - uint64_t Reserved : 30; + uint32_t MWAITEnumerationSupported : 1; + uint32_t InterruptsAsBreakEvent : 1; + uint32_t Reserved : 30; }; uint64_t raw; } ECX; @@ -355,12 +409,12 @@ namespace CPU { struct { - uint64_t C0 : 4; - uint64_t C1 : 4; - uint64_t C2 : 4; - uint64_t C3 : 4; - uint64_t C4 : 4; - uint64_t Reserved : 12; + uint32_t C0 : 4; + uint32_t C1 : 4; + uint32_t C2 : 4; + uint32_t C3 : 4; + uint32_t C4 : 4; + uint32_t Reserved : 12; }; uint64_t raw; } EDX; @@ -369,12 +423,21 @@ namespace CPU /** @brief Thermal and power management information */ struct CPUID0x00000006 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t SensorSupported : 1; - uint64_t Reserved : 31; + uint32_t SensorSupported : 1; + uint32_t Reserved : 31; }; uint64_t raw; } EAX; @@ -383,8 +446,8 @@ namespace CPU { struct { - uint64_t InterruptThreshold : 4; - uint64_t Reserved : 26; + uint32_t InterruptThreshold : 4; + uint32_t Reserved : 26; }; uint64_t raw; } EBX; @@ -393,8 +456,8 @@ namespace CPU { struct { - uint64_t ACNT_MCNT : 1; - uint64_t Reserved : 31; + uint32_t ACNT_MCNT : 1; + uint32_t Reserved : 31; }; uint64_t raw; } ECX; @@ -403,7 +466,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -412,11 +475,20 @@ namespace CPU /** @brief Extended feature flags enumeration */ struct CPUID0x00000007_0 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EAX; @@ -426,69 +498,69 @@ namespace CPU struct { /** @brief Access to base of fs and gs */ - uint64_t FSGSBase : 1; + uint32_t FSGSBase : 1; /** @brief IA32_TSC_ADJUST MSR */ - uint64_t IA32TSCAdjust : 1; + uint32_t IA32TSCAdjust : 1; /** @brief Software Guard Extensions */ - uint64_t SGX : 1; + uint32_t SGX : 1; /** @brief Bit Manipulation Instruction Set 1 */ - uint64_t BMI1 : 1; + uint32_t BMI1 : 1; /** @brief TSX Hardware Lock Elision */ - uint64_t HLE : 1; + uint32_t HLE : 1; /** @brief Advanced Vector Extensions 2 */ - uint64_t AVX2 : 1; + uint32_t AVX2 : 1; /** @brief FDP_EXCPTN_ONLY */ - uint64_t FDPExcptonOnly : 1; + uint32_t FDPExcptonOnly : 1; /** @brief Supervisor Mode Execution Protection */ - uint64_t SMEP : 1; + uint32_t SMEP : 1; /** @brief Bit Manipulation Instruction Set 2 */ - uint64_t BMI2 : 1; + uint32_t BMI2 : 1; /** @brief Enhanced REP MOVSB/STOSB */ - uint64_t ERMS : 1; + uint32_t ERMS : 1; /** @brief INVPCID */ - uint64_t INVPCID : 1; + uint32_t INVPCID : 1; /** @brief RTM */ - uint64_t RTM : 1; + uint32_t RTM : 1; /** @brief Intel Resource Director Monitoring */ - uint64_t RDT_M : 1; + uint32_t RDT_M : 1; /** @brief Deprecates FPU CS and DS values */ - uint64_t DeprecatesFPU : 1; + uint32_t DeprecatesFPU : 1; /** @brief Intel Memory Protection Extensions */ - uint64_t MPX : 1; + uint32_t MPX : 1; /** @brief Intel Resource Director Allocation */ - uint64_t RDT_A : 1; + uint32_t RDT_A : 1; /** @brief AVX-512 Foundation */ - uint64_t AVX512F : 1; + uint32_t AVX512F : 1; /** @brief AVX-512 Doubleword and Quadword Instructions */ - uint64_t AVX512DQ : 1; + uint32_t AVX512DQ : 1; /** @brief RDSEED */ - uint64_t RDSEED : 1; + uint32_t RDSEED : 1; /** @brief Intel Multi-Precision Add-Carry Instruction Extensions */ - uint64_t ADX : 1; + uint32_t ADX : 1; /** @brief Supervisor Mode Access Prevention */ - uint64_t SMAP : 1; + uint32_t SMAP : 1; /** @brief AVX-512 Integer Fused Multiply-Add Instructions */ - uint64_t AVX512IFMA : 1; + uint32_t AVX512IFMA : 1; /** @brief Reserved */ - uint64_t Reserved : 1; + uint32_t Reserved : 1; /** @brief CLFLUSHOPT */ - uint64_t CLFLUSHOPT : 1; + uint32_t CLFLUSHOPT : 1; /** @brief CLWB */ - uint64_t CLWB : 1; + uint32_t CLWB : 1; /** @brief Intel Processor Trace */ - uint64_t IntelProcessorTrace : 1; + uint32_t IntelProcessorTrace : 1; /** @brief AVX-512 Prefetch Instructions */ - uint64_t AVX512PF : 1; + uint32_t AVX512PF : 1; /** @brief AVX-512 Exponential and Reciprocal Instructions */ - uint64_t AVX512ER : 1; + uint32_t AVX512ER : 1; /** @brief AVX-512 Conflict Detection Instructions */ - uint64_t AVX512CD : 1; + uint32_t AVX512CD : 1; /** @brief SHA Extensions */ - uint64_t SHA : 1; + uint32_t SHA : 1; /** @brief AVX-512 Byte and Word Instructions */ - uint64_t AVX512BW : 1; + uint32_t AVX512BW : 1; /** @brief AVX-512 Vector Length Extensions */ - uint64_t AVX512VL : 1; + uint32_t AVX512VL : 1; }; uint64_t raw; } EBX; @@ -498,59 +570,59 @@ namespace CPU struct { /** @brief PREFETCHWT1 */ - uint64_t PREFETCHWT1 : 1; + uint32_t PREFETCHWT1 : 1; /** @brief AVX-512 Vector Bit Manipulation Instructions */ - uint64_t AVX512VBMI : 1; + uint32_t AVX512VBMI : 1; /** @brief User Mode Instruction Prevention */ - uint64_t UMIP : 1; + uint32_t UMIP : 1; /** @brief Memory Protection Keys for User-mode pages */ - uint64_t PKU : 1; + uint32_t PKU : 1; /** @brief PKU enabled by OS */ - uint64_t OSPKE : 1; + uint32_t OSPKE : 1; /** @brief Timed pause and user-level monitor/wait */ - uint64_t WaitPKG : 1; + uint32_t WaitPKG : 1; /** @brief AVX-512 Vector Bit Manipulation Instructions 2 */ - uint64_t AVX512VBMI2 : 1; + uint32_t AVX512VBMI2 : 1; /** @brief Control flow enforcement (CET) shadow stack */ - uint64_t CET_SS : 1; + uint32_t CET_SS : 1; /** @brief Galois Field instructions */ - uint64_t GFNI : 1; + uint32_t GFNI : 1; /** @brief Vector AES instruction set (VEX-256/EVEX) */ - uint64_t VAES : 1; + uint32_t VAES : 1; /** @brief CLMUL instruction set (VEX-256/EVEX) */ - uint64_t VPCLMULQDQ : 1; + uint32_t VPCLMULQDQ : 1; /** @brief AVX-512 Vector Neural Network Instructions */ - uint64_t AVX512VNNI : 1; + uint32_t AVX512VNNI : 1; /** @brief AVX-512 Bit Algorithms Instructions */ - uint64_t AVX512BITALG : 1; + uint32_t AVX512BITALG : 1; /** @brief IA32_TME related MSRs */ - uint64_t TME : 1; + uint32_t TME : 1; /** @brief AVX-512 Vector Population Count Double and Quad-word */ - uint64_t AVX512VPOPCNTDQ : 1; + uint32_t AVX512VPOPCNTDQ : 1; /** @brief Reserved */ - uint64_t Reserved0 : 1; + uint32_t Reserved0 : 1; /** @brief 5-level paging (57 address bits) */ - uint64_t LA57 : 1; + uint32_t LA57 : 1; /** @brief The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX Intel MPX instructions in 64-bit mode */ - uint64_t MAWAU : 5; + uint32_t MAWAU : 5; /** @brief Read Processor ID and IA32_TSC_AUX */ - uint64_t RDPID : 1; + uint32_t RDPID : 1; /** @brief Key Locker */ - uint64_t KL : 1; + uint32_t KL : 1; /** @brief BUS_LOCK_DETECT */ - uint64_t BusLockDetect : 1; + uint32_t BusLockDetect : 1; /** @brief Cache line demote */ - uint64_t CLDEMOTE : 1; + uint32_t CLDEMOTE : 1; /** @brief Reserved */ - uint64_t Reserved1 : 1; + uint32_t Reserved1 : 1; /** @brief MOVDIRI */ - uint64_t MOVDIRI : 1; + uint32_t MOVDIRI : 1; /** @brief MOVDIR64B */ - uint64_t MOVDIR64B : 1; + uint32_t MOVDIR64B : 1; /** @brief SGX Launch Configuration */ - uint64_t SGX_LC : 1; + uint32_t SGX_LC : 1; /** @brief Protection Keys for Supervisor-mode pages */ - uint64_t PKS : 1; + uint32_t PKS : 1; }; uint64_t raw; } ECX; @@ -560,67 +632,67 @@ namespace CPU struct { /** @brief Reserved */ - uint64_t Reserved0 : 2; + uint32_t Reserved0 : 2; /** @brief AVX-512 4-register Neural Network Instructions */ - uint64_t AVX512_4VNNIW : 1; + uint32_t AVX512_4VNNIW : 1; /** @brief AVX-512 4-register Multiply Accumulation Single Precision */ - uint64_t AVX512_4FMAPS : 1; + uint32_t AVX512_4FMAPS : 1; /** @brief Fast Short REP MOVSB/STOSB */ - uint64_t FSRM : 1; + uint32_t FSRM : 1; /** @brief User Inter-Processor Interrupts */ - uint64_t UINTR : 1; + uint32_t UINTR : 1; /** @brief Reserved */ - uint64_t Reserved1 : 2; + uint32_t Reserved1 : 2; /** @brief AVX-512 VP2INTERSECT Doubleword and Quadword Instructions */ - uint64_t AVX512_VP2INTERSECT : 1; + uint32_t AVX512_VP2INTERSECT : 1; /** @brief Special Register Buffer Data Sampling Mitigations */ - uint64_t SRBDS_CTRL : 1; + uint32_t SRBDS_CTRL : 1; /** @brief VERW instruction clears CPU buffers */ - uint64_t MC_CLEAR : 1; + uint32_t MC_CLEAR : 1; /** @brief All TSX transactions are aborted */ - uint64_t TSX_FORCE_ABORT : 1; + uint32_t TSX_FORCE_ABORT : 1; /** @brief Reserved */ - uint64_t Reserved2 : 1; + uint32_t Reserved2 : 1; /** @brief TSX_FORCE_ABORT MSR is available */ - uint64_t TsxForceAbortMsr : 1; + uint32_t TsxForceAbortMsr : 1; /** @brief SERIALIZE */ - uint64_t SERIALIZE : 1; + uint32_t SERIALIZE : 1; /** @brief Mixture of CPU types in processor topology */ - uint64_t HYBRID : 1; + uint32_t HYBRID : 1; /** @brief TSXLDTRK */ - uint64_t TSXLDTRK : 1; + uint32_t TSXLDTRK : 1; /** @brief Reserved */ - uint64_t Reserved3 : 1; + uint32_t Reserved3 : 1; /** @brief Platform configuration for Memory Encryption Technologies Instrctuions */ - uint64_t PCONFIG : 1; + uint32_t PCONFIG : 1; /** @brief Architectural Last Branch Records */ - uint64_t LBR : 1; + uint32_t LBR : 1; /** @brief Control flow enforcement (CET) indirect branch tracking */ - uint64_t CET_IBT : 1; + uint32_t CET_IBT : 1; /** @brief Reserved */ - uint64_t Reserved4 : 1; + uint32_t Reserved4 : 1; /** @brief Tile computation on bfloat16 numbers */ - uint64_t AMX_BF16 : 1; + uint32_t AMX_BF16 : 1; /** @brief AVX512-FP16 half-precision floating-point instructions */ - uint64_t AVX512_FP16 : 1; + uint32_t AVX512_FP16 : 1; /** @brief Tile architecture */ - uint64_t AMX_TILE : 1; + uint32_t AMX_TILE : 1; /** @brief Tile computation on 8-bit integers */ - uint64_t AMX_INT8 : 1; + uint32_t AMX_INT8 : 1; /** @brief Speculation Control, part of Indirect Branch Control (IBC): Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Prediction Barrier (IBPB) */ - uint64_t SPEC_CTRL : 1; + uint32_t SPEC_CTRL : 1; /** @brief Single Thread Indirect Branch Predictor, part of IBC */ - uint64_t STIBP : 1; + uint32_t STIBP : 1; /** @brief IA32_FLUSH_CMD MSR */ - uint64_t L1D_FLUSH : 1; + uint32_t L1D_FLUSH : 1; /** @brief IA32_ARCH_CAPABILITIES (lists speculative side channel mitigations */ - uint64_t ArchCapabilities : 1; + uint32_t ArchCapabilities : 1; /** @brief IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities) */ - uint64_t CoreCapabilities : 1; + uint32_t CoreCapabilities : 1; /** @brief Speculative Store Bypass Disable, as mitigation for Speculative Store Bypass (IA32_SPEC_CTRL) */ - uint64_t SSBD : 1; + uint32_t SSBD : 1; }; uint64_t raw; } EDX; @@ -629,53 +701,62 @@ namespace CPU /** @brief Extended feature flags enumeration */ struct CPUID0x00000007_1 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Reserved0 : 3; + uint32_t Reserved0 : 3; /** @brief RAO-INT */ - uint64_t RAO_INT : 1; + uint32_t RAO_INT : 1; /** @brief AVX Vector Neural Network Instructions (XNNI) (VEX encoded) */ - uint64_t AVX_VNNI : 1; + uint32_t AVX_VNNI : 1; /** @brief AVX-512 instructions for bfloat16 numbers */ - uint64_t AVX512_BF16 : 1; + uint32_t AVX512_BF16 : 1; /** @brief Reserved */ - uint64_t Reserved1 : 1; + uint32_t Reserved1 : 1; /** @brief CMPccXADD */ - uint64_t CMPCCXADD : 1; + uint32_t CMPCCXADD : 1; /** @brief Architectural Performance Monitoring Extended Leaf (EAX=23h) */ - uint64_t ARCHPERFMONEXT : 1; + uint32_t ARCHPERFMONEXT : 1; /** @brief Reserved */ - uint64_t Reserved2 : 1; + uint32_t Reserved2 : 1; /** @brief Fast zero-length MOVSB */ - uint64_t FAST_ZERO_REP_MOVSB : 1; + uint32_t FAST_ZERO_REP_MOVSB : 1; /** @brief Fast zero-length STOSB */ - uint64_t FAST_SHORT_REP_STOSB : 1; + uint32_t FAST_SHORT_REP_STOSB : 1; /** @brief Fast zero-length CMPSB and SCASB */ - uint64_t FAST_SHORT_REP_CMPSB_SCASB : 1; + uint32_t FAST_SHORT_REP_CMPSB_SCASB : 1; /** @brief Reserved */ - uint64_t Reserved3 : 4; + uint32_t Reserved3 : 4; /** @brief Flexible Return and Event Delivery */ - uint64_t FRED : 1; + uint32_t FRED : 1; /** @brief LKGS Instruction */ - uint64_t LKGS : 1; + uint32_t LKGS : 1; /** @brief WRMSRNS instruction */ - uint64_t WRMSRNS : 1; + uint32_t WRMSRNS : 1; /** @brief Reserved */ - uint64_t Reserved4 : 1; + uint32_t Reserved4 : 1; /** @brief AMX instructions for FP16 numbers */ - uint64_t AMX_FP16 : 1; + uint32_t AMX_FP16 : 1; /** @brief HRESET instruction, IA32_HRESET_ENABLE MSR, and Processor History Reset Leaf (EAX=20h) */ - uint64_t HRESET : 1; + uint32_t HRESET : 1; /** @brief AVX IFMA instructions */ - uint64_t AVX_IFMA : 1; + uint32_t AVX_IFMA : 1; /** @brief Reserved */ - uint64_t Reserved5 : 2; + uint32_t Reserved5 : 2; /** @brief Linear Address Masking */ - uint64_t LAM : 1; + uint32_t LAM : 1; /** @brief RDMSRLIST and WRMSRLIST instructions, and the IA32_BARRIER MSR */ - uint64_t MSRLIST : 1; + uint32_t MSRLIST : 1; }; uint64_t raw; } EAX; @@ -685,9 +766,9 @@ namespace CPU struct { /** @brief IA32_PPIN and IA32_PPIN_CTL MSRs */ - uint64_t PPIN : 1; + uint32_t PPIN : 1; /** @brief Reserved */ - uint64_t Reserved : 31; + uint32_t Reserved : 31; }; uint64_t raw; } EBX; @@ -697,7 +778,7 @@ namespace CPU struct { /** @brief Reserved */ - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -707,17 +788,17 @@ namespace CPU struct { /** @brief Reserved */ - uint64_t Reserved0 : 4; + uint32_t Reserved0 : 4; /** @brief AVX VNNI INT8 instructions */ - uint64_t AVX_VNNI_INT8 : 1; + uint32_t AVX_VNNI_INT8 : 1; /** @brief AVX NE CONVERT instructions */ - uint64_t AVX_NE_CONVERT : 1; + uint32_t AVX_NE_CONVERT : 1; /** @brief Reserved */ - uint64_t Reserved1 : 8; + uint32_t Reserved1 : 8; /** @brief PREFETCHIT0 and PREFETCHIT1 instructions */ - uint64_t PREFETCHIT : 1; + uint32_t PREFETCHIT : 1; /** @brief Reserved */ - uint64_t Reserved2 : 17; + uint32_t Reserved2 : 17; }; uint64_t raw; } EDX; @@ -726,14 +807,23 @@ namespace CPU /** @brief Performance monitors */ struct CPUID0x0000000A { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t VersionID : 8; - uint64_t NumberCounters : 8; - uint64_t BitWidthOfCounters : 8; - uint64_t LengthOfEBXBitVector : 8; + uint32_t VersionID : 8; + uint32_t NumberCounters : 8; + uint32_t BitWidthOfCounters : 8; + uint32_t LengthOfEBXBitVector : 8; }; uint64_t raw; } EAX; @@ -742,14 +832,14 @@ namespace CPU { struct { - uint64_t CoreCycles : 1; - uint64_t InstructionsRetired : 1; - uint64_t ReferenceCycles : 1; - uint64_t CacheReferences : 1; - uint64_t CacheMisses : 1; - uint64_t BranchInstructionsRetired : 1; - uint64_t BranchMissesRetired : 1; - uint64_t Reserved : 25; + uint32_t CoreCycles : 1; + uint32_t InstructionsRetired : 1; + uint32_t ReferenceCycles : 1; + uint32_t CacheReferences : 1; + uint32_t CacheMisses : 1; + uint32_t BranchInstructionsRetired : 1; + uint32_t BranchMissesRetired : 1; + uint32_t Reserved : 25; }; uint64_t raw; } EBX; @@ -758,9 +848,9 @@ namespace CPU { struct { - uint64_t FixedFunctionCounters : 5; - uint64_t CounterWidth : 8; - uint64_t Reserved : 19; + uint32_t FixedFunctionCounters : 5; + uint32_t CounterWidth : 8; + uint32_t Reserved : 19; }; uint64_t raw; } ECX; @@ -769,7 +859,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -778,14 +868,23 @@ namespace CPU /** @brief Get CPU frequency information */ struct CPUID0x00000015 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t VersionID : 8; - uint64_t NumberCounters : 8; - uint64_t BitWidthOfCounters : 8; - uint64_t LengthOfEBXBitVector : 8; + uint32_t VersionID : 8; + uint32_t NumberCounters : 8; + uint32_t BitWidthOfCounters : 8; + uint32_t LengthOfEBXBitVector : 8; }; uint64_t raw; } EAX; @@ -794,14 +893,14 @@ namespace CPU { struct { - uint64_t CoreCycles : 1; - uint64_t InstructionsRetired : 1; - uint64_t ReferenceCycles : 1; - uint64_t CacheReferences : 1; - uint64_t CacheMisses : 1; - uint64_t BranchInstructionsRetired : 1; - uint64_t BranchMissesRetired : 1; - uint64_t Reserved : 25; + uint32_t CoreCycles : 1; + uint32_t InstructionsRetired : 1; + uint32_t ReferenceCycles : 1; + uint32_t CacheReferences : 1; + uint32_t CacheMisses : 1; + uint32_t BranchInstructionsRetired : 1; + uint32_t BranchMissesRetired : 1; + uint32_t Reserved : 25; }; uint64_t raw; } EBX; @@ -810,9 +909,9 @@ namespace CPU { struct { - uint64_t FixedFunctionCounters : 5; - uint64_t CounterWidth : 8; - uint64_t Reserved : 19; + uint32_t FixedFunctionCounters : 5; + uint32_t CounterWidth : 8; + uint32_t Reserved : 19; }; uint64_t raw; } ECX; @@ -821,7 +920,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -830,6 +929,15 @@ namespace CPU /** @brief Get CPU frequency information */ struct CPUID0x00000016 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -839,7 +947,7 @@ namespace CPU * * @note TSC frequency = core crystal clock frequency * EBX/EAX */ - uint64_t Denominator : 31; + uint32_t Denominator : 31; }; uint64_t raw; } EAX; @@ -853,7 +961,7 @@ namespace CPU * * @note TSC frequency = core crystal clock frequency * EBX/EAX */ - uint64_t Numerator : 31; + uint32_t Numerator : 31; }; uint64_t raw; } EBX; @@ -863,7 +971,7 @@ namespace CPU struct { /** @brief Core crystal clock frequency in Hz */ - uint64_t CoreCrystalClock : 31; + uint32_t CoreCrystalClock : 31; }; uint64_t raw; } ECX; @@ -873,7 +981,7 @@ namespace CPU struct { /** @brief Reserved */ - uint64_t Reserved : 31; + uint32_t Reserved : 31; }; uint64_t raw; } EDX; @@ -882,11 +990,20 @@ namespace CPU /** @brief Extended CPU information */ struct CPUID0x80000000 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t HighestExtendedFunctionSupported : 32; + uint32_t HighestExtendedFunctionSupported : 32; }; uint64_t raw; } EAX; @@ -895,7 +1012,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -904,7 +1021,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -913,7 +1030,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -923,11 +1040,20 @@ namespace CPU /** @brief Extended CPU information */ struct CPUID0x80000001 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t Unknown : 32; + uint32_t Unknown : 32; }; uint64_t raw; } EAX; @@ -936,7 +1062,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -945,8 +1071,8 @@ namespace CPU { struct { - uint64_t LAHF_SAHF : 1; - uint64_t Reserved : 31; + uint32_t LAHF_SAHF : 1; + uint32_t Reserved : 31; }; uint64_t raw; } ECX; @@ -955,13 +1081,13 @@ namespace CPU { struct { - uint64_t Reserved0 : 11; - uint64_t SYSCALL : 1; - uint64_t Reserved1 : 8; - uint64_t ExecuteDisable : 1; - uint64_t Reserved2 : 8; - uint64_t EMT64T : 1; - uint64_t Reserved3 : 2; + uint32_t Reserved0 : 11; + uint32_t SYSCALL : 1; + uint32_t Reserved1 : 8; + uint32_t ExecuteDisable : 1; + uint32_t Reserved2 : 8; + uint32_t EMT64T : 1; + uint32_t Reserved3 : 2; }; uint64_t raw; } EDX; @@ -971,6 +1097,15 @@ namespace CPU /** @brief CPU brand string */ struct CPUID0x80000002 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -1012,6 +1147,15 @@ namespace CPU /** @brief CPU brand string */ struct CPUID0x80000003 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -1053,6 +1197,15 @@ namespace CPU /** @brief CPU brand string */ struct CPUID0x80000004 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct @@ -1094,14 +1247,23 @@ namespace CPU /** @brief CPU cache line information */ struct CPUID0x80000006 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t InstructionCount : 12; - uint64_t InstructionAssociativity : 4; - uint64_t DataCount : 12; - uint64_t DataAssociativity : 4; + uint32_t InstructionCount : 12; + uint32_t InstructionAssociativity : 4; + uint32_t DataCount : 12; + uint32_t DataAssociativity : 4; }; uint64_t raw; } EAX; @@ -1110,10 +1272,10 @@ namespace CPU { struct { - uint64_t InstructionCount : 12; - uint64_t InstructionAssociativity : 4; - uint64_t DataCount : 12; - uint64_t DataAssociativity : 4; + uint32_t InstructionCount : 12; + uint32_t InstructionAssociativity : 4; + uint32_t DataCount : 12; + uint32_t DataAssociativity : 4; }; uint64_t raw; } EBX; @@ -1122,10 +1284,10 @@ namespace CPU { struct { - uint64_t LineSize : 8; - uint64_t LinePerTag : 4; - uint64_t Associativity : 4; - uint64_t CacheSize : 16; + uint32_t LineSize : 8; + uint32_t LinePerTag : 4; + uint32_t Associativity : 4; + uint32_t CacheSize : 16; }; uint64_t raw; } ECX; @@ -1134,7 +1296,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -1144,13 +1306,22 @@ namespace CPU /** @brief Virtual and physical memory size */ struct CPUID0x80000008 { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t PhysicalAddressBits : 8; - uint64_t LinearAddressBits : 8; - uint64_t Reserved : 16; + uint32_t PhysicalAddressBits : 8; + uint32_t LinearAddressBits : 8; + uint32_t Reserved : 16; }; uint64_t raw; } EAX; @@ -1159,7 +1330,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -1168,7 +1339,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -1177,7 +1348,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -1187,12 +1358,21 @@ namespace CPU /** @brief Secure virtual machine parameters */ struct CPUID0x8000000A { + void Get() + { +#if defined(a64) || defined(a32) + asmv("cpuid" + : "=a"(EAX.raw), "=b"(EBX.raw), "=c"(ECX.raw), "=d"(EDX.raw) + : "a"(0x1)); +#endif // a64 || a32 + } + union { struct { - uint64_t SVMRevision : 8; - uint64_t Reserved : 24; + uint32_t SVMRevision : 8; + uint32_t Reserved : 24; }; uint64_t raw; } EAX; @@ -1201,7 +1381,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EBX; @@ -1210,7 +1390,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } ECX; @@ -1219,7 +1399,7 @@ namespace CPU { struct { - uint64_t Reserved : 32; + uint32_t Reserved : 32; }; uint64_t raw; } EDX; @@ -1229,4 +1409,4 @@ namespace CPU } } -#endif // !__FENNIX_KERNEL_CPU_x64_CPUID_INTEL_H__ +#endif // !__FENNIX_KERNEL_CPU_x86_CPUID_INTEL_H__ diff --git a/include/cpu/x86/x32/cpuid_amd.hpp b/include/cpu/x86/x32/cpuid_amd.hpp deleted file mode 100644 index 9ab0d1d..0000000 --- a/include/cpu/x86/x32/cpuid_amd.hpp +++ /dev/null @@ -1,627 +0,0 @@ -/* - This file is part of Fennix Kernel. - - Fennix Kernel is free software: you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation, either version 3 of - the License, or (at your option) any later version. - - Fennix Kernel is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with Fennix Kernel. If not, see . -*/ - -#ifndef __FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__ -#define __FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__ - -#include - -namespace CPU -{ - namespace x32 - { - /** @brief EXPERIMENTAL IMPLEMENTATION */ - namespace AMD - { - /** @brief Basic CPU information */ - struct CPUID0x0 - { - union - { - struct - { - uint32_t HighestFunctionSupported : 32; - }; - uint32_t raw; - } EAX; - union - { - struct - { - char Vendor[4]; - }; - uint32_t raw; - } EBX; - union - { - struct - { - char Vendor[4]; - }; - uint32_t raw; - } ECX; - union - { - struct - { - char Vendor[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Additional CPU information */ - struct CPUID0x1 - { - union - { - struct - { - uint32_t SteppingID : 4; - uint32_t ModelID : 4; - uint32_t FamilyID : 4; - uint32_t Reserved0 : 4; - uint32_t ExtendedModel : 4; - uint32_t ExtendedFamily : 8; - uint32_t Reserved1 : 4; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t BrandIndex : 8; - uint32_t CLFLUSHLineSize : 8; - uint32_t LogicalProcessorsPerPackage : 8; - uint32_t LocalAPICID : 8; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t SSE3 : 1; - uint32_t Reserved0 : 1; - uint32_t MONITOR : 1; - uint32_t Reserved1 : 1; - uint32_t DS_CPL : 1; - uint32_t Reserved2 : 1; - uint32_t SMX : 1; - uint32_t Reserved3 : 1; - uint32_t TM2 : 1; - uint32_t Reserved4 : 1; - uint32_t CNXT_ID : 1; - uint32_t Reserved5 : 1; - uint32_t CMPXCHG16B : 1; - uint32_t Reserved6 : 1; - uint32_t xTPRUpdateControl : 1; - uint32_t Reserved7 : 1; - uint32_t Reserved8 : 1; - uint32_t DCA : 1; - uint32_t Reserved9 : 1; - uint32_t SSE4_1 : 1; - uint32_t SSE4_2 : 1; - uint32_t Reserved10 : 1; - uint32_t MOVBE : 1; - uint32_t POPCNT : 1; - uint32_t Reserved11 : 1; - uint32_t AES : 1; - uint32_t Reserved12 : 1; - uint32_t XSAVE : 1; - uint32_t OSXSAVE : 1; - uint32_t AVX : 1; - uint32_t Reserved13 : 1; - uint32_t RDRAND : 1; - uint32_t Reserved14 : 1; - uint32_t Hypervisor : 1; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t FPU : 1; - uint32_t VME : 1; - uint32_t DE : 1; - uint32_t PSE : 1; - uint32_t TSC : 1; - uint32_t MSR : 1; - uint32_t PAE : 1; - uint32_t MCE : 1; - uint32_t CX8 : 1; - uint32_t APIC : 1; - uint32_t Reserved0 : 1; - uint32_t SEP : 1; - uint32_t MTRR : 1; - uint32_t PGE : 1; - uint32_t MCA : 1; - uint32_t CMOV : 1; - uint32_t PAT : 1; - uint32_t PSE36 : 1; - uint32_t PSN : 1; - uint32_t CLFSH : 1; - uint32_t Reserved1 : 1; - uint32_t DS : 1; - uint32_t ACPI : 1; - uint32_t MMX : 1; - uint32_t FXSR : 1; - uint32_t SSE : 1; - uint32_t SSE2 : 1; - uint32_t SS : 1; - uint32_t HTT : 1; - uint32_t TM : 1; - uint32_t Reserved2 : 1; - uint32_t PBE : 1; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU cache and TLB */ - struct CPUID0x2 - { - union - { - struct - { - uint32_t L1DataCacheSize : 8; - uint32_t L1DataCacheAssociativity : 8; - uint32_t L1DataCacheLineSize : 8; - uint32_t L1DataCachePartitions : 8; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t L1InstructionCacheSize : 8; - uint32_t L1InstructionCacheAssociativity : 8; - uint32_t L1InstructionCacheLineSize : 8; - uint32_t L1InstructionCachePartitions : 8; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t L2UnifiedCacheSize : 16; - uint32_t L2UnifiedCacheAssociativity : 8; - uint32_t L2UnifiedCacheLineSize : 8; - uint32_t L2UnifiedCachePartitions : 8; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t L3UnifiedCacheSize : 18; - uint32_t L3UnifiedCacheAssociativity : 8; - uint32_t L3UnifiedCacheLineSize : 8; - uint32_t L3UnifiedCachePartitions : 8; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Get CPU hypervisor information */ - struct CPUID0x40000000 - { - union - { - struct - { - /** - * @brief Maximum input value for hypervisor CPUID information. - * @note Can be from 0x40000001 to 0x400000FF - */ - uint32_t MaximumInputValue : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Extended CPU information */ - struct CPUID0x80000001 - { - union - { - struct - { - uint32_t SteppingID : 4; - uint32_t ModelID : 4; - uint32_t FamilyID : 4; - uint32_t Reserved0 : 4; - uint32_t ExtendedModel : 4; - uint32_t ExtendedFamily : 8; - uint32_t Reserved1 : 4; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t BranchID : 16; - uint32_t Reserved0 : 16; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t LAHF_SAHF : 1; - uint32_t CmpLegacy : 1; - uint32_t SVM : 1; - uint32_t Reserved0 : 1; - uint32_t AltMovCr8 : 1; - uint32_t Reserved1 : 26; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t FPU : 1; - uint32_t VME : 1; - uint32_t DE : 1; - uint32_t PSE : 1; - uint32_t TSC : 1; - uint32_t MSR : 1; - uint32_t PAE : 1; - uint32_t MCE : 1; - uint32_t CMPXCHG8B : 1; - uint32_t APIC : 1; - uint32_t Reserved0 : 1; - uint32_t SYSCALL : 1; - uint32_t MTRR : 1; - uint32_t PGE : 1; - uint32_t MCA : 1; - uint32_t CMOV : 1; - uint32_t PAT : 1; - uint32_t PSE36 : 1; - uint32_t Reserved1 : 1; - uint32_t ExeDisable : 1; - uint32_t Reserved2 : 1; - uint32_t MMXExtended : 1; - uint32_t MMX : 1; - uint32_t FXSR : 1; - uint32_t FFXSR : 1; - uint32_t Reserved3 : 1; - uint32_t RDTSCP : 1; - uint32_t Reserved4 : 1; - uint32_t LongMode : 1; - uint32_t ThreeDNowExtended : 1; - uint32_t ThreeDNow : 1; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000002 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000003 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000004 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Cache and TLB information */ - struct CPUID0x80000005 - { - union - { - struct - { - uint32_t InstructionCount : 8; - uint32_t InstructionAssociativity : 8; - uint32_t DataCount : 8; - uint32_t DataAssociativity : 8; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t InstructionCount : 8; - uint32_t InstructionAssociativity : 8; - uint32_t DataCount : 8; - uint32_t DataAssociativity : 8; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t LineSize : 8; - uint32_t LinePerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t LineSize : 8; - uint32_t LinePerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU cache line information */ - struct CPUID0x80000006 - { - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t LineSize : 8; - uint32_t LinePerTag : 4; - uint32_t Associativity : 4; - uint32_t CacheSize : 16; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief APM */ - struct CPUID0x80000007 - { - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t TemperatureSensor : 1; - uint32_t FrequencyID : 1; - uint32_t VoltageID : 1; - uint32_t ThermaTrip : 1; - uint32_t HarwareThermalControl : 1; - uint32_t SoftwareThermalControl : 1; - uint32_t Reserved0 : 2; - uint32_t TSCInvariant : 1; - uint32_t Reserved1 : 23; - }; - uint32_t raw; - } EDX; - }; - } - } -} - -#endif // !__FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__ diff --git a/include/cpu/x86/x32/cpuid_intel.hpp b/include/cpu/x86/x32/cpuid_intel.hpp deleted file mode 100644 index 02accd9..0000000 --- a/include/cpu/x86/x32/cpuid_intel.hpp +++ /dev/null @@ -1,965 +0,0 @@ -/* - This file is part of Fennix Kernel. - - Fennix Kernel is free software: you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation, either version 3 of - the License, or (at your option) any later version. - - Fennix Kernel is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with Fennix Kernel. If not, see . -*/ - -#ifndef __FENNIX_KERNEL_CPU_x32_CPUID_INTEL_H__ -#define __FENNIX_KERNEL_CPU_x32_CPUID_INTEL_H__ - -#include - -namespace CPU -{ - namespace x32 - { - /** @brief EXPERIMENTAL IMPLEMENTATION */ - namespace Intel - { - /** @brief Basic CPU information */ - struct CPUID0x0 - { - union - { - struct - { - uint32_t HighestFunctionSupported : 32; - }; - uint32_t raw; - } EAX; - union - { - struct - { - char rbx[4]; - }; - uint32_t raw; - } EBX; - union - { - struct - { - char rcx[4]; - }; - uint32_t raw; - } ECX; - union - { - struct - { - char rdx[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Additional CPU information */ - struct CPUID0x1 - { - union - { - struct - { - uint32_t SteppingID : 4; - uint32_t ModelID : 4; - uint32_t FamilyID : 4; - uint32_t Type : 2; - uint32_t Reserved0 : 2; - uint32_t ExtendedModel : 4; - uint32_t ExtendedFamily : 8; - uint32_t Reserved1 : 4; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t BrandIndex : 8; - uint32_t CLFLUSHLineSize : 8; - uint32_t LogicalProcessorsPerPackage : 8; - uint32_t LocalAPICID : 8; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t SSE3 : 1; - uint32_t PCLMULQDQ : 1; - uint32_t DTES64 : 1; - uint32_t MONITOR : 1; - uint32_t DS_CPL : 1; - uint32_t VMX : 1; - uint32_t SMX : 1; - uint32_t EIST : 1; - uint32_t TM2 : 1; - uint32_t SSSE3 : 1; - uint32_t CNXT_ID : 1; - uint32_t Reserved0 : 1; - uint32_t FMA : 1; - uint32_t CMPXCHG16B : 1; - uint32_t xTPRUpdateControl : 1; - uint32_t PDCM : 1; - uint32_t Reserved1 : 1; - uint32_t PCID : 1; - uint32_t DCA : 1; - uint32_t SSE4_1 : 1; - uint32_t SSE4_2 : 1; - uint32_t x2APIC : 1; - uint32_t MOVBE : 1; - uint32_t POPCNT : 1; - uint32_t TSCDeadline : 1; - uint32_t AES : 1; - uint32_t XSAVE : 1; - uint32_t OSXSAVE : 1; - uint32_t AVX : 1; - uint32_t F16C : 1; - uint32_t RDRAND : 1; - uint32_t Reserved2 : 1; - uint32_t Hypervisor : 1; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t FPU : 1; - uint32_t VME : 1; - uint32_t DE : 1; - uint32_t PSE : 1; - uint32_t TSC : 1; - uint32_t MSR : 1; - uint32_t PAE : 1; - uint32_t MCE : 1; - uint32_t CX8 : 1; - uint32_t APIC : 1; - uint32_t Reserved0 : 1; - uint32_t SEP : 1; - uint32_t MTRR : 1; - uint32_t PGE : 1; - uint32_t MCA : 1; - uint32_t CMOV : 1; - uint32_t PAT : 1; - uint32_t PSE36 : 1; - uint32_t PSN : 1; - uint32_t CLFSH : 1; - uint32_t Reserved1 : 1; - uint32_t DS : 1; - uint32_t ACPI : 1; - uint32_t MMX : 1; - uint32_t FXSR : 1; - uint32_t SSE : 1; - uint32_t SSE2 : 1; - uint32_t SS : 1; - uint32_t HTT : 1; - uint32_t TM : 1; - uint32_t Reserved2 : 1; - uint32_t PBE : 1; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU cache and TLB */ - struct CPUID0x2 - { - union - { - struct - { - uint32_t CacheLineSize : 8; - uint32_t CacheLinesPerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t CacheLineSize : 8; - uint32_t CacheLinesPerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t CacheLineSize : 8; - uint32_t CacheLinesPerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t CacheLineSize : 8; - uint32_t CacheLinesPerTag : 8; - uint32_t Associativity : 8; - uint32_t CacheSize : 8; - }; - uint32_t raw; - } EDX; - }; - - /** @brief CPU serial number */ - struct CPUID0x3 - { - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t ProcessorSerialNumber : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t ProcessorSerialNumber : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Cache information */ - struct CPUID0x4_1 - { - union - { - struct - { - uint32_t Type : 5; - uint32_t Level : 3; - uint32_t SelfInitializing : 1; - uint32_t FullyAssociative : 1; - uint32_t Reserved : 4; - uint32_t MaxAddressableIdsForLogicalProcessors : 12; - uint32_t CoresPerPackage : 6; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t SystemCoherencyLineSize : 12; - uint32_t PhysicalLinePartitions : 10; - uint32_t WaysOfAssociativity : 10; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief MONITOR information */ - struct CPUID0x5 - { - union - { - struct - { - uint32_t SmallestMonitorLineSize : 16; - uint32_t Reserved : 16; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t LargestMonitorLineSize : 16; - uint32_t Reserved : 16; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t MWAITEnumerationSupported : 1; - uint32_t InterruptsAsBreakEvent : 1; - uint32_t Reserved : 30; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t C0 : 4; - uint32_t C1 : 4; - uint32_t C2 : 4; - uint32_t C3 : 4; - uint32_t C4 : 4; - uint32_t Reserved : 12; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Thermal and power management information */ - struct CPUID0x6 - { - union - { - struct - { - uint32_t SensorSupported : 1; - uint32_t Reserved : 31; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t InterruptThreshold : 4; - uint32_t Reserved : 26; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t ACNT_MCNT : 1; - uint32_t Reserved : 31; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Performance monitors */ - struct CPUID0xA - { - union - { - struct - { - uint32_t VersionID : 8; - uint32_t NumberCounters : 8; - uint32_t BitWidthOfCounters : 8; - uint32_t LengthOfEBXBitVector : 8; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t CoreCycles : 1; - uint32_t InstructionsRetired : 1; - uint32_t ReferenceCycles : 1; - uint32_t CacheReferences : 1; - uint32_t CacheMisses : 1; - uint32_t BranchInstructionsRetired : 1; - uint32_t BranchMissesRetired : 1; - uint32_t Reserved : 25; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t FixedFunctionCounters : 5; - uint32_t CounterWidth : 8; - uint32_t Reserved : 19; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Get CPU frequency information */ - struct CPUID0x15 - { - union - { - struct - { - uint32_t VersionID : 8; - uint32_t NumberCounters : 8; - uint32_t BitWidthOfCounters : 8; - uint32_t LengthOfEBXBitVector : 8; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t CoreCycles : 1; - uint32_t InstructionsRetired : 1; - uint32_t ReferenceCycles : 1; - uint32_t CacheReferences : 1; - uint32_t CacheMisses : 1; - uint32_t BranchInstructionsRetired : 1; - uint32_t BranchMissesRetired : 1; - uint32_t Reserved : 25; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t FixedFunctionCounters : 5; - uint32_t CounterWidth : 8; - uint32_t Reserved : 19; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Get CPU frequency information */ - struct CPUID0x16 - { - union - { - struct - { - /** - * @brief Denominator of the TSC frequency - * - * @note TSC frequency = core crystal clock frequency * EBX/EAX - */ - uint32_t Denominator : 31; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - /** - * @brief Numerator of the TSC frequency - * - * @note TSC frequency = core crystal clock frequency * EBX/EAX - */ - uint32_t Numerator : 31; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - /** @brief Core crystal clock frequency in Hz */ - uint32_t CoreCrystalClock : 31; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - /** @brief Reserved */ - uint32_t Reserved : 31; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Get CPU hypervisor information */ - struct CPUID0x40000000 - { - union - { - struct - { - /** - * @brief Maximum input value for hypervisor CPUID information. - * @note Can be from 0x40000001 to 0x400000FF - */ - uint32_t MaximumInputValue : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - /** @brief Hypervisor vendor signature */ - char Hypervisor[4]; - }; - uint32_t raw; - } EDX; - }; - - /** @brief Extended CPU information */ - struct CPUID0x80000000 - { - union - { - struct - { - uint32_t HighestExtendedFunctionSupported : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief Extended CPU information */ - struct CPUID0x80000001 - { - union - { - struct - { - uint32_t Unknown : 32; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t LAHF_SAHF : 1; - uint32_t Reserved : 31; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved0 : 11; - uint32_t SYSCALL : 1; - uint32_t Reserved1 : 8; - uint32_t ExecuteDisable : 1; - uint32_t Reserved2 : 8; - uint32_t EMT64T : 1; - uint32_t Reserved3 : 2; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000002 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000003 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief CPU brand string */ - struct CPUID0x80000004 - { - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - char Brand[4]; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief CPU cache line information */ - struct CPUID0x80000006 - { - union - { - struct - { - uint32_t InstructionCount : 12; - uint32_t InstructionAssociativity : 4; - uint32_t DataCount : 12; - uint32_t DataAssociativity : 4; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t InstructionCount : 12; - uint32_t InstructionAssociativity : 4; - uint32_t DataCount : 12; - uint32_t DataAssociativity : 4; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t LineSize : 8; - uint32_t LinePerTag : 4; - uint32_t Associativity : 4; - uint32_t CacheSize : 16; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief Virtual and physical memory size */ - struct CPUID0x80000008 - { - union - { - struct - { - uint32_t PhysicalAddressBits : 8; - uint32_t LinearAddressBits : 8; - uint32_t Reserved : 16; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - - /** @brief Secure virtual machine parameters */ - struct CPUID0x8000000A - { - union - { - struct - { - uint32_t SVMRevision : 8; - uint32_t Reserved : 24; - }; - uint32_t raw; - } EAX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EBX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } ECX; - - union - { - struct - { - uint32_t Reserved : 32; - }; - uint32_t raw; - } EDX; - uint32_t raw; - }; - } - } -} - -#endif // !__FENNIX_KERNEL_CPU_x32_CPUID_INTEL_H__