Fennix/Kernel
1
0
Fork 0
mirror of https://github.com/Fennix-Project/Kernel.git synced 2025-05-28 15:34:33 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Signal all cores to stop on exception

Browse Source
This commit is contained in:
Alex 2023-02-19 00:51:44 +02:00
parent c5e3809674
commit 73e5f13d35
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
3 changed files with 36 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Architecture/amd64/cpu/InterruptDescriptorTable.cpp
View File

@ -284,7 +284,7 @@ namespace InterruptDescriptorTable
INTERRUPT_HANDLER(0x3a)
INTERRUPT_HANDLER(0x3b)
INTERRUPT_HANDLER(0x3c)
INTERRUPT_HANDLER(0x3d)
EXCEPTION_HANDLER(0x3d)
/* Free */

38
Core/Crash/CrashHandler.cpp
View File

@ -15,8 +15,10 @@
#if defined(__amd64__)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#include "../Architecture/amd64/cpu/apic.hpp"
#elif defined(__i386__)
#include "../../Architecture/i686/cpu/gdt.hpp"
#include "../Architecture/i686/cpu/apic.hpp"
#elif defined(__aarch64__)
#endif
@ -719,18 +721,43 @@ namespace CrashHandler
Display->SetBuffer(SBIdx);
}
SafeFunction void StopAllCores()
{
#if defined(__amd64__) || defined(__i386__)
if (SMP::CPUCores > 1)
{
CPU::Interrupts(CPU::Enable);
for (int i = 1; i < SMP::CPUCores; i++)
{
locked_debug("Sending IPI to CPU %d", i);
APIC::InterruptCommandRegisterLow icr;
icr.Vector = CPU::x64::IRQ29;
icr.Level = APIC::APICLevel::Assert;
((APIC::APIC *)Interrupts::apic[0])->IPI(i, icr);
__sync;
}
CPU::Interrupts(CPU::Disable);
}
#elif defined(__aarch64__)
#endif
}
SafeFunction void Handle(void *Data)
{
// TODO: SUPPORT SMP
CPU::Interrupts(CPU::Disable);
error("An exception occurred!");
for (size_t i = 0; i < INT_FRAMES_MAX; i++)
EHIntFrames[i] = Interrupts::InterruptFrames[i];
SBIdx = 255;
CHArchTrapFrame *Frame = (CHArchTrapFrame *)Data;
#if defined(__amd64__)
if (Frame->InterruptNumber == CPU::x64::IRQ29)
{
locked_error("CPU %d halted.", GetCurrentCPU()->ID);
CPU::Stop();
}
error("An exception occurred!");
error("Exception: %#llx", Frame->InterruptNumber);
for (size_t i = 0; i < INT_FRAMES_MAX; i++)
EHIntFrames[i] = Interrupts::InterruptFrames[i];
PageFaultAddress = CPU::x64::readcr2().PFLA;
if (Frame->cs != GDT_USER_CODE && Frame->cs != GDT_USER_DATA)
@ -740,6 +767,7 @@ namespace CrashHandler
TaskManager->Panic();
ForceUnlock = true;
Display->CreateBuffer(0, 0, SBIdx);
StopAllCores();
}
else
{
@ -749,6 +777,7 @@ namespace CrashHandler
{
ForceUnlock = true;
Display->CreateBuffer(0, 0, SBIdx);
StopAllCores();
EHPrint("\eFF0000Cannot get CPU data! This results in a kernel crash!");
error("Cannot get CPU data! This results in a kernel crash!");
error("This should never happen!");
@ -763,6 +792,7 @@ namespace CrashHandler
TaskManager->Panic();
ForceUnlock = true;
Display->CreateBuffer(0, 0, SBIdx);
StopAllCores();
}
else
{

2
include/cpu.hpp
View File

@ -2661,7 +2661,7 @@ namespace CPU
IRQ26 = 0x3a,
IRQ27 = 0x3b,
IRQ28 = 0x3c,
IRQ29 = 0x3d,
IRQ29 = 0x3d, // Reserved for icr stop core
/* Free */