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Update GDT & IDT structures
This commit is contained in:
Alex
parent
05610c7e7a
commit
622214003f
GPG Key ID:
EACC3AD603BAB4DD
@ -25,117 +25,84 @@
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namespace GlobalDescriptorTable
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{
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static GlobalDescriptorTableEntries GDTEntriesTemplate = {
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.Null = {
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.Limit0 = 0x0,
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.BaseLow = 0x0,
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.BaseMiddle = 0x0,
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.Access = {.Raw = 0x0},
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// .Limit1 = 0x0,
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.Flags = {.Raw = 0x0},
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.BaseHigh = 0x0,
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},
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.Null = 0,
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.Code = {
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.Limit0 = 0xFFFF,
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.BaseLow = 0x0,
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.BaseMiddle = 0x0,
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.Access = {
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.A = 0,
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.RW = 1,
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.DC = 0,
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.E = 1,
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.S = 1,
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.DPL = 0,
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.P = 1,
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},
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// .Limit1 = 0xF,
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.Flags = {
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.Reserved = 0xF, /* Workaround for Limit1 */
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.AVL = 0,
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.L = 1,
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.DB = 0,
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.G = 1,
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},
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.BaseHigh = 0x0,
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.SegmentLimitLow = 0xFFFF,
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.BaseAddressLow = 0x0,
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.BaseAddressHigh = 0x0,
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.Accessed = 0,
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.Readable = 1,
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.Conforming = 0,
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.Executable = 1,
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.Type = 1,
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.DescriptorPrivilegeLevel = 0,
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.Present = 1,
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.SegmentLimitHigh = 0xF,
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.Available = 0,
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.Long = 1,
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.Default = 0,
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.Granularity = 1,
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.BaseAddressHigher = 0x0,
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},
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.Data = {
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.Limit0 = 0xFFFF,
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.BaseLow = 0x0,
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.BaseMiddle = 0x0,
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.Access = {
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.A = 0,
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.RW = 1,
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.DC = 0,
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.E = 0,
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.S = 1,
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.DPL = 0,
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.P = 1,
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},
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// .Limit1 = 0xF,
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.Flags = {
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.Reserved = 0xF, /* Workaround for Limit1 */
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.AVL = 0,
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.L = 0,
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.DB = 1,
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.G = 1,
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},
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.BaseHigh = 0x0,
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.SegmentLimitLow = 0xFFFF,
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.BaseAddressLow = 0x0,
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.BaseAddressHigh = 0x0,
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.Accessed = 0,
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.Writable = 1,
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.ExpandDown = 0,
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.Executable = 0,
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.Type = 1,
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.DescriptorPrivilegeLevel = 0,
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.Present = 1,
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.SegmentLimitHigh = 0xF,
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.Available = 0,
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.Reserved = 0,
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.Default = 0,
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.Granularity = 1,
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.BaseAddressHigher = 0x0,
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},
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.UserData = {
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.Limit0 = 0xFFFF,
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.BaseLow = 0x0,
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.BaseMiddle = 0x0,
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.Access = {
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.A = 0,
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.RW = 1,
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.DC = 0,
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.E = 0,
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.S = 1,
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.DPL = 3,
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.P = 1,
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},
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// .Limit1 = 0xF,
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.Flags = {
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.Reserved = 0xF, /* Workaround for Limit1 */
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.AVL = 0,
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.L = 0,
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.DB = 1,
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.G = 1,
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},
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.BaseHigh = 0x0,
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.SegmentLimitLow = 0xFFFF,
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.BaseAddressLow = 0x0,
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.BaseAddressHigh = 0x0,
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.Accessed = 0,
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.Writable = 1,
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.ExpandDown = 1,
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.Executable = 0,
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.Type = 1,
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.DescriptorPrivilegeLevel = 3,
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.Present = 1,
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.SegmentLimitHigh = 0xF,
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.Available = 0,
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.Reserved = 0,
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.Default = 0,
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.Granularity = 1,
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.BaseAddressHigher = 0x0,
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},
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.UserCode = {
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.Limit0 = 0xFFFF,
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.BaseLow = 0x0,
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.BaseMiddle = 0x0,
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.Access = {
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.A = 0,
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.RW = 1,
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.DC = 0,
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.E = 1,
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.S = 1,
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.DPL = 3,
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.P = 1,
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},
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// .Limit1 = 0xF,
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.Flags = {
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.Reserved = 0xF, /* Workaround for Limit1 */
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.AVL = 0,
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.L = 1,
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.DB = 0,
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.G = 1,
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},
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.BaseHigh = 0x0,
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.SegmentLimitLow = 0xFFFF,
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.BaseAddressLow = 0x0,
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.BaseAddressHigh = 0x0,
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.Accessed = 0,
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.Readable = 1,
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.Conforming = 0,
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.Executable = 1,
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.Type = 1,
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.DescriptorPrivilegeLevel = 3,
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.Present = 1,
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.SegmentLimitHigh = 0xF,
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.Available = 0,
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.Long = 1,
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.Default = 0,
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.Granularity = 1,
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.BaseAddressHigher = 0x0,
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},
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.TaskStateSegment = {},
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.TaskStateSegment{},
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};
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GlobalDescriptorTableEntries GDTEntries[MAX_CPU] __aligned(16);
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@ -156,48 +123,18 @@ namespace GlobalDescriptorTable
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SafeFunction void Init(int Core)
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{
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memcpy(&GDTEntries[Core], &GDTEntriesTemplate, sizeof(GlobalDescriptorTableEntries));
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gdt[Core] = {.Length = sizeof(GlobalDescriptorTableEntries) - 1, .Entries = &GDTEntries[Core]};
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gdt[Core] =
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{
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.Limit = sizeof(GlobalDescriptorTableEntries) - 1,
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.BaseAddress = &GDTEntries[Core],
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};
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debug("GDT: %#lx", &gdt[Core]);
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debug("GDT KERNEL: CODE %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
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GDT_KERNEL_CODE,
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GDTEntries[Core].Code.Limit0,
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GDTEntries[Core].Code.BaseLow,
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GDTEntries[Core].Code.BaseMiddle,
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GDTEntries[Core].Code.Access.Raw,
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GDTEntries[Core].Code.Flags.Reserved,
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GDTEntries[Core].Code.Flags.Raw & ~0xF,
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GDTEntries[Core].Code.BaseHigh);
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debug("GDT KERNEL: DATA %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
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GDT_KERNEL_DATA,
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GDTEntries[Core].Data.Limit0,
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GDTEntries[Core].Data.BaseLow,
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GDTEntries[Core].Data.BaseMiddle,
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GDTEntries[Core].Data.Access.Raw,
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GDTEntries[Core].Data.Flags.Reserved,
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GDTEntries[Core].Data.Flags.Raw & ~0xF,
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GDTEntries[Core].Data.BaseHigh);
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debug("GDT USER: CODE %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
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GDT_USER_CODE,
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GDTEntries[Core].UserCode.Limit0,
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GDTEntries[Core].UserCode.BaseLow,
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GDTEntries[Core].UserCode.BaseMiddle,
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GDTEntries[Core].UserCode.Access.Raw,
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GDTEntries[Core].UserCode.Flags.Reserved,
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GDTEntries[Core].UserCode.Flags.Raw & ~0xF,
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GDTEntries[Core].UserCode.BaseHigh);
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debug("GDT USER: DATA %#lx: Limit0: 0x%X, BaseLow: 0x%X, BaseMiddle: 0x%X, Access: 0x%X, Limit1: 0x%X, Flags: 0x%X, BaseHigh: 0x%X",
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GDT_USER_DATA,
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GDTEntries[Core].UserData.Limit0,
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GDTEntries[Core].UserData.BaseLow,
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GDTEntries[Core].UserData.BaseMiddle,
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GDTEntries[Core].UserData.Access.Raw,
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GDTEntries[Core].UserData.Flags.Reserved,
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GDTEntries[Core].UserData.Flags.Raw & ~0xF,
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GDTEntries[Core].UserData.BaseHigh);
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debug("GDT KERNEL CODE %#lx", GDT_KERNEL_CODE);
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debug("GDT KERNEL DATA %#lx", GDT_KERNEL_DATA);
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debug("GDT USER CODE %#lx", GDT_USER_CODE);
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debug("GDT USER DATA %#lx", GDT_USER_DATA);
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debug("GDT TSS %#lx", GDT_TSS);
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CPU::x64::lgdt(&gdt[Core]);
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@ -222,13 +159,22 @@ namespace GlobalDescriptorTable
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uintptr_t Base = (uintptr_t)&tss[Core];
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size_t Limit = Base + sizeof(TaskStateSegment);
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gdt[Core].Entries->TaskStateSegment.Limit = Limit & 0xFFFF;
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gdt[Core].Entries->TaskStateSegment.BaseLow = Base & 0xFFFF;
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gdt[Core].Entries->TaskStateSegment.BaseMiddle = (Base >> 16) & 0xFF;
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gdt[Core].Entries->TaskStateSegment.BaseHigh = (Base >> 24) & 0xFF;
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gdt[Core].Entries->TaskStateSegment.BaseUpper = s_cst(uint32_t, (Base >> 32) & 0xFFFFFFFF);
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gdt[Core].Entries->TaskStateSegment.Access = {.A = 1, .RW = 0, .DC = 0, .E = 1, .S = 0, .DPL = 0, .P = 1};
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gdt[Core].Entries->TaskStateSegment.Granularity = (0 << 4) | ((Limit >> 16) & 0xF);
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SystemSegmentDescriptor *tssDesc = &gdt[Core].BaseAddress->TaskStateSegment;
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tssDesc->SegmentLimitLow = Limit & 0xFFFF;
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tssDesc->BaseAddressLow = Base & 0xFFFF;
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tssDesc->BaseAddressMiddle = (Base >> 16) & 0xFF;
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tssDesc->Type = AVAILABLE_64BIT_TSS;
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tssDesc->Zero0 = 0;
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tssDesc->DescriptorPrivilegeLevel = 0;
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tssDesc->Present = 1;
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tssDesc->Available = 0;
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tssDesc->Reserved0 = 0;
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tssDesc->Granularity = 0;
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tssDesc->BaseAddressHigh = (Base >> 24) & 0xFF;
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tssDesc->BaseAddressHigher = s_cst(uint32_t, (Base >> 32) & 0xFFFFFFFF);
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tssDesc->Reserved1 = 0;
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tssDesc->Zero1 = 0;
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tssDesc->Reserved2 = 0;
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tss[Core].IOMapBaseAddressOffset = sizeof(TaskStateSegment);
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tss[Core].StackPointer[0] = (uint64_t)CPUStackPointer[Core] + STACK_SIZE;
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@ -19,100 +19,10 @@
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#define __FENNIX_KERNEL_GDT_H__
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#include <types.h>
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#include <cpu/x86/x64/SegmentDescriptors.hpp>
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namespace GlobalDescriptorTable
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{
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struct TaskStateSegmentEntry
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{
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/* LOW */
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uint16_t Limit;
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uint16_t BaseLow;
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uint8_t BaseMiddle;
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union GlobalDescriptorTableAccess
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{
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struct
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{
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/**
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* Access bit.
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*
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* @note The CPU sets this bit to 1 when the segment
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* is accessed.
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*/
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uint8_t A : 1;
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/**
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* Readable bit for code segments, writable bit for data
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* segments.
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*
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* Code Segment:
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* This bit must be 1 for the segment to be readable.
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*
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* Data Segment:
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* This bit must be 1 for the segment to be writable.
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*/
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uint8_t RW : 1;
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/**
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* Direction bit for data segments, conforming bit for
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* code segments.
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*
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* Code Segment:
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* This bit must be 1 for code in the segment to be
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* able to be executed from an equal or lower privilege
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* level.
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*
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* Data Segment:
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* This bit must be 1 for the segment to grow up (higher
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* addresses).
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*/
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uint8_t DC : 1;
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/**
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* Executable bit.
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*
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* This bit must be 1 for code-segment descriptors.
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*
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* This bit must be 0 for data-segment and system
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* descriptors.
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*/
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uint8_t E : 1;
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/**
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* Descriptor type.
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*
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* This bit must be 0 for system descriptors.
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*
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* This bit must be 1 for code or data segment
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* descriptor.
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*/
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uint8_t S : 1;
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/**
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* Descriptor privilege level.
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*
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* This field determines the privilege level of the
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* segment.
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*
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* 0 = kernel mode
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* 3 = user mode
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*/
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uint8_t DPL : 2;
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/**
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* Present bit.
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*
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* This bit must be 1 for all valid descriptors.
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*/
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uint8_t P : 1;
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} __packed;
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uint8_t Raw : 8;
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} Access;
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uint8_t Granularity;
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uint8_t BaseHigh;
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/* HIGH */
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uint32_t BaseUpper;
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uint32_t Reserved;
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} __packed;
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struct TaskStateSegment
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{
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@ -125,189 +35,20 @@ namespace GlobalDescriptorTable
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uint16_t IOMapBaseAddressOffset;
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} __packed;
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struct GlobalDescriptorTableEntry
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{
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/**
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* Limit 0:15
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*/
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uint16_t Limit0 : 16;
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/**
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* Low Base 0:15
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*/
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uint16_t BaseLow : 16;
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/**
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* Middle Base 16:23
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*/
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uint8_t BaseMiddle : 8;
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/**
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* Access
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*/
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union GlobalDescriptorTableAccess
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{
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struct
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{
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/**
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* Access bit.
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*
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* @note The CPU sets this bit to 1 when the segment
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* is accessed.
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*/
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uint8_t A : 1;
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/**
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* Readable bit for code segments, writable bit for
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* data segments.
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*
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* Code Segment:
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* This bit must be 1 for the segment to be readable.
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*
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* Data Segment:
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* This bit must be 1 for the segment to be writable.
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*/
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uint8_t RW : 1;
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/**
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* Direction bit for data segments, conforming bit for
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* code segments.
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*
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* Code Segment:
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* This bit must be 1 for code in the segment to be able
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* to be executed from an equal or lower privilege level.
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*
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* Data Segment:
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* This bit must be 1 for the segment to grow up (higher
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* addresses).
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*/
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uint8_t DC : 1;
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/**
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* Executable bit.
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*
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* This bit must be 1 for code-segment descriptors.
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*
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* This bit must be 0 for data-segment and
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* system descriptors.
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*/
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uint8_t E : 1;
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/**
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* Descriptor type.
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*
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* This bit must be 0 for system descriptors.
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*
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* This bit must be 1 for code or data segment
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* descriptor.
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*/
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uint8_t S : 1;
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/**
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* Descriptor privilege level.
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*
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* This field determines the privilege level of the
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* segment.
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*
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* 0 = kernel mode
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* 3 = user mode
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*/
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uint8_t DPL : 2;
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/**
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* Present bit.
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*
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* This bit must be 1 for all valid descriptors.
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*/
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uint8_t P : 1;
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} __packed;
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uint8_t Raw : 8;
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} Access;
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// /** Limit 16:19 */
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// uint16_t Limit1 : 4;
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/**
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* Flags
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*/
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union GlobalDescriptorTableFlags
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{
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struct
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{
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/* FIXME: Without this, the kernel crashes. */
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uint8_t Reserved : 4;
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/**
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* Available bit.
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*
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* This bit is available for use by system software.
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*/
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uint8_t AVL : 1;
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/**
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* Long mode.
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*
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* If the long mode bit is clear, the segment is in
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* 32-bit protected mode.
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*
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* If the long mode bit is set, the segment is in
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* 64-bit long mode.
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*/
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uint8_t L : 1;
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/**
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* Size flag.
|
||||
*
|
||||
* If the size bit is clear, the segment is in
|
||||
* 16-bit protected mode.
|
||||
*
|
||||
* If the size bit is set, the segment is in
|
||||
* 32-bit protected mode.
|
||||
*/
|
||||
uint8_t DB : 1;
|
||||
|
||||
/**
|
||||
* Granularity bit.
|
||||
*
|
||||
* If the granularity bit is clear, the segment limit
|
||||
* is in 1 B blocks.
|
||||
*
|
||||
* If the granularity bit is set, the segment limit is
|
||||
* in 4 KiB blocks.
|
||||
*/
|
||||
uint8_t G : 1;
|
||||
} __packed;
|
||||
uint8_t Raw : 8;
|
||||
} Flags;
|
||||
|
||||
/**
|
||||
* High Base 24:31
|
||||
*/
|
||||
uint8_t BaseHigh : 8;
|
||||
} __packed;
|
||||
|
||||
struct GlobalDescriptorTableEntries
|
||||
{
|
||||
GlobalDescriptorTableEntry Null;
|
||||
GlobalDescriptorTableEntry Code;
|
||||
GlobalDescriptorTableEntry Data;
|
||||
GlobalDescriptorTableEntry UserData;
|
||||
GlobalDescriptorTableEntry UserCode;
|
||||
TaskStateSegmentEntry TaskStateSegment;
|
||||
uint64_t Null;
|
||||
CodeSegmentDescriptor Code;
|
||||
DataSegmentDescriptor Data;
|
||||
DataSegmentDescriptor UserData;
|
||||
CodeSegmentDescriptor UserCode;
|
||||
SystemSegmentDescriptor TaskStateSegment;
|
||||
} __packed;
|
||||
|
||||
struct GlobalDescriptorTableDescriptor
|
||||
{
|
||||
/**
|
||||
* GDT entries length
|
||||
*/
|
||||
uint16_t Length;
|
||||
|
||||
/**
|
||||
* GDT entries address
|
||||
*/
|
||||
GlobalDescriptorTableEntries *Entries;
|
||||
uint16_t Limit;
|
||||
GlobalDescriptorTableEntries *BaseAddress;
|
||||
} __packed;
|
||||
|
||||
extern void *CPUStackPointer[];
|
||||
|
||||
@ -19,109 +19,10 @@
|
||||
#define __FENNIX_KERNEL_IDT_H__
|
||||
|
||||
#include <types.h>
|
||||
#include <cpu/x86/x64/SegmentDescriptors.hpp>
|
||||
|
||||
namespace InterruptDescriptorTable
|
||||
{
|
||||
/**
|
||||
* Manual: AMD Architecture Programmer's Manual Volume 2: System Programming
|
||||
* Subsection: 4.8.3 System Descriptors
|
||||
* Table: 4-6
|
||||
*
|
||||
* @note Reserved values are not listed in the table.
|
||||
*/
|
||||
enum GateType
|
||||
{
|
||||
LDT_64BIT = 0b0010,
|
||||
AVAILABLE_64BIT_TSS = 0b1001,
|
||||
BUSY_64BIT_TSS = 0b1011,
|
||||
CALL_GATE_64BIT = 0b1100,
|
||||
INTERRUPT_GATE_64BIT = 0b1110,
|
||||
TRAP_GATE_64BIT = 0b1111,
|
||||
};
|
||||
|
||||
enum PrivilegeLevelType
|
||||
{
|
||||
RING0 = 0b0,
|
||||
RING1 = 0b1,
|
||||
RING2 = 0b10,
|
||||
RING3 = 0b11,
|
||||
};
|
||||
|
||||
enum InterruptStackTableType
|
||||
{
|
||||
IST0 = 0b0,
|
||||
IST1 = 0b1,
|
||||
IST2 = 0b10,
|
||||
IST3 = 0b11,
|
||||
IST4 = 0b100,
|
||||
IST5 = 0b101,
|
||||
IST6 = 0b110,
|
||||
};
|
||||
|
||||
struct InterruptGate
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t TargetOffsetLow : 16;
|
||||
uint64_t TargetSelector : 16;
|
||||
/* +4 */
|
||||
uint64_t InterruptStackTable : 3;
|
||||
uint64_t Reserved0 : 5;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t TargetOffsetMiddle : 16;
|
||||
/* +8 */
|
||||
uint64_t TargetOffsetHigh : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 32;
|
||||
} __packed;
|
||||
|
||||
typedef InterruptGate TrapGate;
|
||||
|
||||
struct CallGate
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t TargetOffsetLow : 16;
|
||||
uint64_t TargetSelector : 16;
|
||||
/* +4 */
|
||||
uint64_t Reserved0 : 8;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero0 : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t TargetOffsetMiddle : 16;
|
||||
/* +8 */
|
||||
uint64_t TargetOffsetHigh : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 8;
|
||||
uint64_t Zero1 : 5;
|
||||
uint64_t Reserved2 : 19;
|
||||
} __packed;
|
||||
|
||||
struct SystemSegmentDescriptor
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t SegmentLimitLow : 16;
|
||||
uint64_t BaseAddressLow : 16;
|
||||
/* +4 */
|
||||
uint64_t BaseAddressMiddle : 8;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero0 : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t SegmentLimitMiddle : 4;
|
||||
uint64_t Available : 1;
|
||||
uint64_t Reserved0 : 2;
|
||||
uint64_t Granularity : 1;
|
||||
uint64_t BaseAddressHigh : 8;
|
||||
/* +8 */
|
||||
uint64_t BaseAddressHigher : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 8;
|
||||
uint64_t Zero1 : 5;
|
||||
uint64_t Reserved2 : 19;
|
||||
} __packed;
|
||||
|
||||
union IDTGateDescriptor
|
||||
{
|
||||
|
||||
168
include/cpu/x86/x64/SegmentDescriptors.hpp
Normal file
168
include/cpu/x86/x64/SegmentDescriptors.hpp
Normal file
@ -0,0 +1,168 @@
|
||||
/*
|
||||
This file is part of Fennix Kernel.
|
||||
|
||||
Fennix Kernel is free software: you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation, either version 3 of
|
||||
the License, or (at your option) any later version.
|
||||
|
||||
Fennix Kernel is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
|
||||
#define __FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
/**
|
||||
* Manual: AMD Architecture Programmer's Manual Volume 2: System Programming
|
||||
* Subsection: 4.8.3 System Descriptors
|
||||
* Table: 4-6
|
||||
*
|
||||
* @note Reserved values are not listed in the table.
|
||||
*/
|
||||
enum GateType
|
||||
{
|
||||
LDT_64BIT = 0b0010,
|
||||
AVAILABLE_64BIT_TSS = 0b1001,
|
||||
BUSY_64BIT_TSS = 0b1011,
|
||||
CALL_GATE_64BIT = 0b1100,
|
||||
INTERRUPT_GATE_64BIT = 0b1110,
|
||||
TRAP_GATE_64BIT = 0b1111,
|
||||
};
|
||||
|
||||
enum PrivilegeLevelType
|
||||
{
|
||||
RING0 = 0b0,
|
||||
RING1 = 0b1,
|
||||
RING2 = 0b10,
|
||||
RING3 = 0b11,
|
||||
};
|
||||
|
||||
enum InterruptStackTableType
|
||||
{
|
||||
IST0 = 0b0,
|
||||
IST1 = 0b1,
|
||||
IST2 = 0b10,
|
||||
IST3 = 0b11,
|
||||
IST4 = 0b100,
|
||||
IST5 = 0b101,
|
||||
IST6 = 0b110,
|
||||
};
|
||||
|
||||
struct InterruptGate
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t TargetOffsetLow : 16;
|
||||
uint64_t TargetSelector : 16;
|
||||
/* +4 */
|
||||
uint64_t InterruptStackTable : 3;
|
||||
uint64_t Reserved0 : 5;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t TargetOffsetMiddle : 16;
|
||||
/* +8 */
|
||||
uint64_t TargetOffsetHigh : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 32;
|
||||
} __packed;
|
||||
|
||||
typedef InterruptGate TrapGate;
|
||||
|
||||
struct CallGate
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t TargetOffsetLow : 16;
|
||||
uint64_t TargetSelector : 16;
|
||||
/* +4 */
|
||||
uint64_t Reserved0 : 8;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero0 : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t TargetOffsetMiddle : 16;
|
||||
/* +8 */
|
||||
uint64_t TargetOffsetHigh : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 8;
|
||||
uint64_t Zero1 : 5;
|
||||
uint64_t Reserved2 : 19;
|
||||
} __packed;
|
||||
|
||||
struct SystemSegmentDescriptor
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t SegmentLimitLow : 16;
|
||||
uint64_t BaseAddressLow : 16;
|
||||
/* +4 */
|
||||
uint64_t BaseAddressMiddle : 8;
|
||||
uint64_t Type : 4;
|
||||
uint64_t Zero0 : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t SegmentLimitMiddle : 4;
|
||||
uint64_t Available : 1;
|
||||
uint64_t Reserved0 : 2;
|
||||
uint64_t Granularity : 1;
|
||||
uint64_t BaseAddressHigh : 8;
|
||||
/* +8 */
|
||||
uint64_t BaseAddressHigher : 32;
|
||||
/* +12 */
|
||||
uint64_t Reserved1 : 8;
|
||||
uint64_t Zero1 : 5;
|
||||
uint64_t Reserved2 : 19;
|
||||
} __packed;
|
||||
|
||||
struct CodeSegmentDescriptor
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t SegmentLimitLow : 16;
|
||||
uint64_t BaseAddressLow : 16;
|
||||
/* +4 */
|
||||
uint64_t BaseAddressHigh : 8;
|
||||
uint64_t Accessed : 1;
|
||||
uint64_t Readable : 1;
|
||||
uint64_t Conforming : 1;
|
||||
uint64_t Executable : 1;
|
||||
uint64_t Type : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t SegmentLimitHigh : 4;
|
||||
uint64_t Available : 1;
|
||||
uint64_t Long : 1;
|
||||
uint64_t Default : 1;
|
||||
uint64_t Granularity : 1;
|
||||
uint64_t BaseAddressHigher : 8;
|
||||
} __packed;
|
||||
|
||||
struct DataSegmentDescriptor
|
||||
{
|
||||
/* +0 */
|
||||
uint64_t SegmentLimitLow : 16;
|
||||
uint64_t BaseAddressLow : 16;
|
||||
/* +4 */
|
||||
uint64_t BaseAddressHigh : 8;
|
||||
uint64_t Accessed : 1;
|
||||
uint64_t Writable : 1;
|
||||
uint64_t ExpandDown : 1;
|
||||
uint64_t Executable : 1;
|
||||
uint64_t Type : 1;
|
||||
uint64_t DescriptorPrivilegeLevel : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t SegmentLimitHigh : 4;
|
||||
uint64_t Available : 1;
|
||||
uint64_t Reserved : 1;
|
||||
uint64_t Default : 1;
|
||||
uint64_t Granularity : 1;
|
||||
uint64_t BaseAddressHigher : 8;
|
||||
} __packed;
|
||||
|
||||
#endif // !__FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
|
||||
Loading…
x
Reference in New Issue
Block a user