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Update GDT & IDT structures
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168
include/cpu/x86/x64/SegmentDescriptors.hpp
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168
include/cpu/x86/x64/SegmentDescriptors.hpp
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
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#define __FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
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#include <types.h>
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/**
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* Manual: AMD Architecture Programmer's Manual Volume 2: System Programming
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* Subsection: 4.8.3 System Descriptors
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* Table: 4-6
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*
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* @note Reserved values are not listed in the table.
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*/
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enum GateType
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{
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LDT_64BIT = 0b0010,
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AVAILABLE_64BIT_TSS = 0b1001,
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BUSY_64BIT_TSS = 0b1011,
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CALL_GATE_64BIT = 0b1100,
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INTERRUPT_GATE_64BIT = 0b1110,
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TRAP_GATE_64BIT = 0b1111,
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};
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enum PrivilegeLevelType
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{
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RING0 = 0b0,
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RING1 = 0b1,
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RING2 = 0b10,
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RING3 = 0b11,
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};
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enum InterruptStackTableType
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{
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IST0 = 0b0,
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IST1 = 0b1,
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IST2 = 0b10,
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IST3 = 0b11,
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IST4 = 0b100,
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IST5 = 0b101,
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IST6 = 0b110,
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};
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struct InterruptGate
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{
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/* +0 */
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uint64_t TargetOffsetLow : 16;
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uint64_t TargetSelector : 16;
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/* +4 */
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uint64_t InterruptStackTable : 3;
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uint64_t Reserved0 : 5;
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uint64_t Type : 4;
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uint64_t Zero : 1;
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uint64_t DescriptorPrivilegeLevel : 2;
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uint64_t Present : 1;
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uint64_t TargetOffsetMiddle : 16;
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/* +8 */
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uint64_t TargetOffsetHigh : 32;
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/* +12 */
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uint64_t Reserved1 : 32;
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} __packed;
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typedef InterruptGate TrapGate;
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struct CallGate
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{
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/* +0 */
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uint64_t TargetOffsetLow : 16;
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uint64_t TargetSelector : 16;
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/* +4 */
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uint64_t Reserved0 : 8;
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uint64_t Type : 4;
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uint64_t Zero0 : 1;
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uint64_t DescriptorPrivilegeLevel : 2;
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uint64_t Present : 1;
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uint64_t TargetOffsetMiddle : 16;
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/* +8 */
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uint64_t TargetOffsetHigh : 32;
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/* +12 */
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uint64_t Reserved1 : 8;
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uint64_t Zero1 : 5;
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uint64_t Reserved2 : 19;
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} __packed;
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struct SystemSegmentDescriptor
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{
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/* +0 */
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uint64_t SegmentLimitLow : 16;
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uint64_t BaseAddressLow : 16;
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/* +4 */
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uint64_t BaseAddressMiddle : 8;
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uint64_t Type : 4;
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uint64_t Zero0 : 1;
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uint64_t DescriptorPrivilegeLevel : 2;
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uint64_t Present : 1;
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uint64_t SegmentLimitMiddle : 4;
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uint64_t Available : 1;
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uint64_t Reserved0 : 2;
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uint64_t Granularity : 1;
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uint64_t BaseAddressHigh : 8;
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/* +8 */
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uint64_t BaseAddressHigher : 32;
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/* +12 */
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uint64_t Reserved1 : 8;
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uint64_t Zero1 : 5;
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uint64_t Reserved2 : 19;
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} __packed;
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struct CodeSegmentDescriptor
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{
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/* +0 */
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uint64_t SegmentLimitLow : 16;
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uint64_t BaseAddressLow : 16;
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/* +4 */
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uint64_t BaseAddressHigh : 8;
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uint64_t Accessed : 1;
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uint64_t Readable : 1;
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uint64_t Conforming : 1;
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uint64_t Executable : 1;
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uint64_t Type : 1;
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uint64_t DescriptorPrivilegeLevel : 2;
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uint64_t Present : 1;
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uint64_t SegmentLimitHigh : 4;
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uint64_t Available : 1;
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uint64_t Long : 1;
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uint64_t Default : 1;
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uint64_t Granularity : 1;
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uint64_t BaseAddressHigher : 8;
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} __packed;
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struct DataSegmentDescriptor
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{
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/* +0 */
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uint64_t SegmentLimitLow : 16;
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uint64_t BaseAddressLow : 16;
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/* +4 */
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uint64_t BaseAddressHigh : 8;
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uint64_t Accessed : 1;
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uint64_t Writable : 1;
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uint64_t ExpandDown : 1;
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uint64_t Executable : 1;
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uint64_t Type : 1;
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uint64_t DescriptorPrivilegeLevel : 2;
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uint64_t Present : 1;
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uint64_t SegmentLimitHigh : 4;
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uint64_t Available : 1;
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uint64_t Reserved : 1;
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uint64_t Default : 1;
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uint64_t Granularity : 1;
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uint64_t BaseAddressHigher : 8;
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} __packed;
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#endif // !__FENNIX_KERNEL_SEGMENT_DESCRIPTORS_H__
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