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Fix compilation issues

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This commit is contained in:
Alex 2023-04-06 18:11:01 +03:00
parent 78d785f1c6
commit 5e5819e3be
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
7 changed files with 60 additions and 58 deletions
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14
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -259,25 +259,27 @@ namespace APIC
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
#endif
// FIXME: Not sure if I configured this correctly or something else is wrong
if (cpuid1amd.ECX.x2APIC)
{
// x2APICSupported = cpuid1amd.ECX.x2APIC;
fixme("AMD does even support x2APIC? ECX->Reserved10: %#lx", cpuid1amd.ECX.Reserved10);
fixme("x2APIC is supported");
}
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"

36
Core/CPU.cpp
View File

@ -205,9 +205,9 @@ namespace CPU
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -222,9 +222,9 @@ namespace CPU
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -377,17 +377,17 @@ namespace CPU
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
if (cpuid1amd.ECX.SSE4_2)
if (cpuid1amd.ECX.SSE42)
SIMDType |= SIMD_SSE42;
else if (cpuid1amd.ECX.SSE4_1)
else if (cpuid1amd.ECX.SSE41)
SIMDType |= SIMD_SSE41;
else if (cpuid1amd.ECX.SSE3)
SIMDType |= SIMD_SSE3;
@ -397,9 +397,9 @@ namespace CPU
SIMDType |= SIMD_SSE;
#ifdef DEBUG
if (cpuid1amd.ECX.SSE4_2)
if (cpuid1amd.ECX.SSE42)
debug("SSE4.2 is supported.");
if (cpuid1amd.ECX.SSE4_1)
if (cpuid1amd.ECX.SSE41)
debug("SSE4.1 is supported.");
if (cpuid1amd.ECX.SSE3)
debug("SSE3 is supported.");
@ -414,9 +414,9 @@ namespace CPU
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
@ -462,18 +462,18 @@ namespace CPU
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
if (Type == SIMD_SSE42)
return cpuid1amd.ECX.SSE4_2;
return cpuid1amd.ECX.SSE42;
else if (Type == SIMD_SSE41)
return cpuid1amd.ECX.SSE4_1;
return cpuid1amd.ECX.SSE41;
else if (Type == SIMD_SSE3)
return cpuid1amd.ECX.SSE3;
else if (Type == SIMD_SSE2)
@ -484,9 +484,9 @@ namespace CPU
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)

24
Core/Random.cpp
View File

@ -28,9 +28,9 @@ namespace Random
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -42,9 +42,9 @@ namespace Random
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -77,9 +77,9 @@ namespace Random
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -91,9 +91,9 @@ namespace Random
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -126,9 +126,9 @@ namespace Random
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -140,9 +140,9 @@ namespace Random
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"

8
Tasking/Task.cpp
View File

@ -804,9 +804,9 @@ namespace Tasking
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -818,9 +818,9 @@ namespace Tasking
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"

8
Tests/RandomNumberGenerator.cpp
View File

@ -27,9 +27,9 @@ __constructor void TestRandom()
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
CPU::x64::AMD::CPUID0x00000001 cpuid1amd;
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
CPU::x32::AMD::CPUID0x00000001 cpuid1amd;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"
@ -41,9 +41,9 @@ __constructor void TestRandom()
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
CPU::x64::Intel::CPUID0x00000001 cpuid1intel;
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
CPU::x32::Intel::CPUID0x00000001 cpuid1intel;
#endif
#if defined(a64) || defined(a32)
asmv("cpuid"

2
include/cpu/x86/x64/cpuid_amd.hpp
View File

@ -537,7 +537,7 @@ namespace CPU
uint64_t Reserved0 : 11;
uint64_t CET_U : 1;
uint64_t CET_S : 1;
uint64_t Reserved0 : 19;
uint64_t Reserved1 : 19;
};
uint64_t raw;
} ECX;

24
include/cpu/x86/x64/cpuid_intel.hpp
View File

@ -28,7 +28,7 @@ namespace CPU
namespace Intel
{
/** @brief Basic CPU information */
struct CPUID0x0
struct CPUID0x00000000
{
union
{
@ -65,7 +65,7 @@ namespace CPU
};
/** @brief Additional CPU information */
struct CPUID0x1
struct CPUID0x00000001
{
union
{
@ -178,7 +178,7 @@ namespace CPU
};
/** @brief CPU cache and TLB */
struct CPUID0x2
struct CPUID0x00000002
{
union
{
@ -230,7 +230,7 @@ namespace CPU
};
/** @brief CPU serial number */
struct CPUID0x3
struct CPUID0x00000003
{
union
{
@ -270,7 +270,7 @@ namespace CPU
};
/** @brief Cache information */
struct CPUID0x4_1
struct CPUID0x00000004_1
{
union
{
@ -318,7 +318,7 @@ namespace CPU
};
/** @brief MONITOR information */
struct CPUID0x5
struct CPUID0x00000005
{
union
{
@ -367,7 +367,7 @@ namespace CPU
};
/** @brief Thermal and power management information */
struct CPUID0x6
struct CPUID0x00000006
{
union
{
@ -410,7 +410,7 @@ namespace CPU
};
/** @brief Extended feature flags enumeration */
struct CPUID0x7_0
struct CPUID0x00000007_0
{
union
{
@ -627,7 +627,7 @@ namespace CPU
};
/** @brief Extended feature flags enumeration */
struct CPUID0x7_1
struct CPUID0x00000007_1
{
union
{
@ -724,7 +724,7 @@ namespace CPU
};
/** @brief Performance monitors */
struct CPUID0xA
struct CPUID0x0000000A
{
union
{
@ -776,7 +776,7 @@ namespace CPU
};
/** @brief Get CPU frequency information */
struct CPUID0x15
struct CPUID0x00000015
{
union
{
@ -828,7 +828,7 @@ namespace CPU
};
/** @brief Get CPU frequency information */
struct CPUID0x16
struct CPUID0x00000016
{
union
{