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Added new kernel param
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@ -74,7 +74,7 @@ namespace Interrupts
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{
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// TODO: This function is called by SMP too. Do not initialize timers that doesn't support multiple cores.
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apic[Core] = new APIC::APIC(Core);
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if (Core == 0) // Redirect IRQs to the BSP
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if (Core == Config.IOAPICInterruptCore) // Redirect IRQs to the specified core.
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((APIC::APIC *)apic[Core])->RedirectIRQs(Core);
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}
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else
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18
KConfig.cpp
18
KConfig.cpp
@ -36,6 +36,12 @@ static struct cag_option ConfigOptions[] = {
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.value_name = "VALUE",
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.description = "Number of cores to use (0 = all; 1 is the first code, not 0)"},
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{.identifier = 'p',
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.access_letters = "pP",
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.access_name = "ioapicirq",
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.value_name = "VALUE",
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.description = "Which core will be used for I/O APIC interrupts"},
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{.identifier = 't',
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.access_letters = "tT",
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.access_name = "tasking",
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@ -77,11 +83,12 @@ KernelConfig ParseConfig(char *Config)
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int argc = 0;
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char **argv = nullptr;
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struct KernelConfig config = {Memory::MemoryAllocatorType::Pages,
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struct KernelConfig config = {Memory::MemoryAllocatorType::XallocV1,
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0,
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{'/', 's', 'y', 's', 't', 'e', 'm', '/', 'd', 'r', 'i', 'v', 'e', 'r', 's', '\0'},
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{'/', 's', 'y', 's', 't', 'e', 'm', '/', 'i', 'n', 'i', 't', '\0'},
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false,
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true,
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0,
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0,
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false};
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@ -320,6 +327,13 @@ ParseSuccess:
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config.Cores = atoi(value);
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break;
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}
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case 'p':
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{
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value = cag_option_get_value(&context);
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KPrint("\eAAFFAARedirecting I/O APIC interrupts to %s%s", atoi(value) ? "core " : "", atoi(value) ? value : "BSP");
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config.IOAPICInterruptCore = atoi(value);
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break;
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}
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case 't':
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{
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value = cag_option_get_value(&context);
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@ -12,6 +12,7 @@ struct KernelConfig
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char InitPath[256];
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bool InterruptsOnCrash;
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int Cores;
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int IOAPICInterruptCore;
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bool UnlockDeadLock;
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};
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